Programmable logic vendors boost tool support

Electronic News, May 1, 1995 by Jim DeTar

SANTA CLARA, CALIF. - Software tools were spotlighted here at the PLD Design Conference and Exhibit (PLDCon `95) last week as at least three companies - Lattice Semiconductor, ICT and QuickLogic - unveiled programmable toolsets and/or plans for near-term introductions. In addition, Lattice introduced the second member of its ispLSI 2000 family of complex programmable logic devices (CPLDs) along with a roadmap for future products.

Lattice announced additional tools support from three companies - Mentor Graphics, OrCAD and Synopsys - vaulting the company from being supported by 25 percent of major tool vendors last year to about 90 percent coverage currently.

"We have worked with the tester companies to put together a smooth tester interface. Even board level test manufacturers have recognized that ISP is an idea whose time has come," said Stan Kopec, Lattice's director of marketing.

Lattice also rolled out the second member of its recently-announced 2,000 gate ispLSI2000 family (EN, Feb. 13), the ispLSI 2064. At 125MHz, the 64-macrocell ispLSI 2064 joins the previously-released 154MH, 32-macrocell ispLSI 2032. AD devices in the family feature Lattice's In-System Programmability (ISP), the ability to program and reprogram logic devices on a printed circuit board.

The ispLSI 2064 features four dedicated input pins, two global output enable pins, three clock input pins and 64 macrocells. The device also contains 16 generic logic blocks (GLBs) with a gate density of 2,000 gates. Logic delay (Tpd) of 7.5 nanoseconds and a maximum operating frequency (Fmax) of 125MHZ make the CPLD suitable for designs requiring high speed. For designs calling for minimal switching noise, it offers independently programmable output slew rate control.

Future versions of the 2000 family - the 96 macrocell ispLSI 2096, and 128 macrocell ispLSI 2128, are expected to surface around midyear. According to Mr. Kopec, the 2096 and 2128 are currently sampling and will be released simultaneously in the June time-frame.

Price in 1,000 piece quantities for the 80MHz ispLSI 2064-80LJ in an 84-pin PLCC package is $11.50; 125, 100 and 80MHz versions are offered in both 84-pin PLCC and 100-pin TQFP packages. All versions are available for shipment immediately, Lattice said.

Meanwhile, ICT expanded software support for its Programmable Electrically Erasable Logic (PEEL) family with a "smart" translator software tool and new fitters. The Smart Translator is said to offer designers automatic programming file translation for a range of 20- to 44-pin simple PLDs and CPLDs, allowing retargeting to ICT PEEL devices and PEEL arrays. In addition, the tool allows designs to be imported into ICT's PLACE software, where they can be modified to integrate more logic or add new features.

Robin Jigour, VP of marketing for ICT, asserted that "Most PLD vendors seem to be abandoning the needs of lower pin-count PLD users, leaving them with obsolete, architecturally-restrictive devices that are relatively expensive and/or limited in supply."

The Smart Translator can automatically convert JEDEC programming files from more than 50 PLD architectures to the programming files for pincompatible PEEL devices and arrays, the company said. The Smart Translator and the fitters for I/O's Synario and ABEL for Windows, and Isdata's LOG/iC are available at no cost to qualified designers.

QuickLogic, which is considering plans to go public by the end of 1996, will roll out its next-generation of FPGA development tools in June. The QuickWorks tools will support the company's existing products, ranging from 1,000 to 8,000 gates, including the 3.3-volt devices introduced last month (EN, April 24). QuickLogic is currently transferring its product line from double layer metal, 1.0-micron, five-inch wafer CMOS production to the triple layer metal, 0.65-micron six-inch process used by its design and manufacturing partner, Cypress Semiconductor.

Ed Smith, QuickLogic's director of marketing, said the June release of QuickLogic's QuickWorks software will include VHDL and Verilog synthesis and simulation capabilities, which are currently available from third-party vendors for QuickLogic FPGAs.

"Using a workstation synthesis tool from a third-party vendor, it took 90 minutes for a 2,000-gate design on a SPARC workstation. With QuickWorks it took 33 seconds to complete the identical utilization," Mr. Smith said. Additional features slated for the June release include Libraries of Parameterized Modules (LPM) which is expected to improve third-party synthesis tool results, and the emerging VITAL standard for VHDL simulation support.

In addition, the company will add frequency driven timing to its tool suite in a future version, although that may not be ready in time for the June release, Mr. Smith noted. And Power Calculator, which will enable application specific power consumption calculation, will be added by the end of the year. Currently, QuickLogic tools support Windows 3.1, Windows NT, Windows 95 and Unix on Sun and HewlettPackard workstations.