Altera marketing program accents logic design-ins

Electronic News, July 10, 1995 by Jim DeTar

SAN JOSE, CALIF.--Altera Corp. will today initiate a program to sell programmable logic in vertical markets, initially for asynchronous transfer mode (ATM) networking chipsets, with the introduction of an ATM Design Kit. Altera said it is also working with a variety of standard ATM chipset vendors, including Brooktree, to ensure its macrocells are compatible with existing chipsets.

An expanding ATM market does not allow designers to wait for standard ATM chipsets to mature as ATM industry standards rapidly shift, according to Cliff Tong, Altera's director of product marketing. "ATM is the networking technology that will take us into the next century. While the standards are still evolving, the road to the marketplace for ATM equipment manufacturers is risky. Programmable logic offers unmatched adaptability, ease of use and performance necessary to meet the needs of the ATM designer while minimizing the company's exposure to risk," he said.

The ATM Design Kit was created to work with Altera's FLEX 8000 family of in-circuit reconfigurable (ICR) complex programmable logic devices (CPLDs). Altera recently completed migrating its FLEX 8000 family to a 0.6-micron triple-layer metal process and began shipping the final model of the family, the 16,000-gate EPF81500A (EN, May 29).

Sandeep Vij, Altera's components product marketing manager, said in an interview that the ATM thrust is the first in a series of vertical market kits Altera will unveil. "This is the next revolution in programmable logic--to go after vertical markets, to give designers the source codes that they can change. We think this is going to be a big trend, and we are the ones kicking it off."

The ATM Design Kit initially provides application notes for two primary building blocks for complex ATM designs. One building block details the implementation of an Altera-designed, highspeed, 16-bit parallel cyclic redundancy checker (CRC)--a common error checker in high-speed networking applications such as ATM. Implemented in the FLEX architecture, a 16-bit CCITT-standard CRC design operates at more than 80MHz. According to Altera, system and card designers can customize a CRC of larger or smaller word size in minutes by modifying the CRC macrofunction.

Another application explores the issue of traffic control, a topic that is currently being examined by the ATM Forum. Altera has been a member of the ATM Forum for about a year now. In order to support a variety of ATM traffic, parameters such as bandwidth, delay and jitter need to be guaranteed. As a result, designers are required to use the appropriate traffic scheduling algorithms for proper resource allocation in ATM switches.

Altera's ATM Design Kit provides a sample ATM packet scheduler design created by Dr. Anujan Varma at the University of California at Santa Cruz (UCSC) and based on a weighted, round-robin scheduling algorithm that schedules input from multiple ports to one output port.

Altera said it provided Dr. Varma with the software to create the algorithm, as well as some grant money for the joint development effort. There is no licensing arrangement, according to Mr. Vij.

The ATM packet scheduler is designed to support up to 32 ATM virtual channel groups with a dedicated buffer of up to 1,024 cells per group. This macrofunction can be modified so variations of the packet scheduler can be modeled and studied to meet individual design requirements.

According to Mr. Vij, these are the first two of a variety of ATM macrofunctions the company plans to offer. "These are the first two real design examples we have. This is really going to be a new trend. We will provide particular design kits in a vertical market."

Mr. Vij admitted that standard parts can be bought for less but contended that programmable logic provides a time-to-market advantage. "Standard chipsets will always provide a less expensive solution than programmable logic. But there are a lot of very volatile areas even with the ATM standard itself--for example, packet standards and the switch standard. The ATM Forum is changing its codes and guidelines on a regular basis."

Altera is also expected to announce support from existing and new customers for the ATM Design Kit, including ZeitNet Inc., a provider of ATM network interface cards which chose the Altera FLEX 8000 as its programmable logic solution. ZeitNet is implementing a high-speed intelligent VRAM controller on a network interface card using a 6,000-gate Altera EPF8636A. In addition to providing an interface between VRAM, CPU and segmentation and reassembly (SAR) devices, the EPF8636A also assists the CPU in reducing the overhead in packet processing, according to Subbu Ganesan, associate director of hardware engineering at Zeitnet.

"Altera FLEX 8000 has met all our critical requirements; even when we use the slowest speed grade we are able to perform partial segmentation and reassembly overhead processing by running a state machine inside the EPF8636A at 50MHz."

Altera is offering the ATM Design Kit at no charge to qualified OEMs.