Vitesse offers new 0.5-micron H-GaAs IV process

Electronic News, July 31, 1995

CAMARILLO, CALIF.--Vitesse Semiconductor, in a bid to nudge gallium arsenide (GaAs) semiconductors closer toward mainstream markets, has unveiled a new process--the 0.5-micron H-GaAs IV digital IC process--that is capable of combining one-million transistor integration with microwave performance. Products using the new process are to be introduced later this year.

Lou Tomasetta, president and CEO, said the H-GaAs IV process offers a low-cost alternative to CMOS. "Vitesse has focused on reducing process cost through improvements in density and manufacturability." This fourth generation Vitesse process provides a VLSI platform designed to enable telecom, datacom and test instrumentation systems at claimed price levels below ECL and BiCMOS technology. It is comparable in price to deep submicron CMOS, Vitesse claims.

Ira Deyhimy, VP of product development, said that the first products based on H-GaAs IV are beginning to be announced. "Prototypes (samples) will be available early 4Q of this year. One of the first product families will be a family of gate arrays called the 'GLX' gate array family. Our current gate array family is the 'FX,' based on H-GaAs III technology. That is in wide use today and we do a lot of business with it. The whole reason for doing H-GaAs IV is to reduce the power by a factor of two. The lower we can make the power in a given technology, the greater opportunities that open up."

Mr. Deyhimy admitted that GaAs has a way to go before it becomes cost-competitive with CMOS in mainstream applications but maintained that the new, lower power H-GaAs IV process is a step in that direction. "One of the beauties of our technology is its utter simplicity. We use off-the-shelf wafers from multiple vendors and do direct ion implantation on these wafers. We can do two layers of metallization with nine mask layers. That is one of the keys to making it cost competitive with other technologies like CMOS."

H-GaAs IV is a 0.5-micron scaled version of the company's H-GaAs III process currently in production. Chip density has been doubled compared to the previous 0.6-micron technology by scaling of the five-layer metal interconnect. The previous-generation H-GaAs III process was four-layer metal. The resulting higher packing density yields smaller, less expensive die in H-GaAs IV. In addition, plastic packaging will replace higher cost ceramic packaging on the new process.

H-GaAs IV implements refractory metal self-aligned gate transistors, one layer of local interconnect and four layers of standard aluminum global interconnect. Polymide dielectrics and planarization are used to reduce interconnect capacitance and regulate routing density.

The basic transistor structure is altered to achieve a transistor cutoff frequency (Ft) in excess of 35GHz and a delay-power product of less than six femto-Joules (fJ), resulting in unloaded gate delays of less than 70 picoseconds.

In an IEEE paper earlier this year, Mr. Deyhimy discussed future implementations of GaAs technology. "Each generation of VLSI technology can outperform its predecessors thanks to reductions in chip geometry. But as features shrink well below 1-micron, electric fields must also be contained by reducing power supply voltages. This last turn of events slows signals in MOS ICs but not--at least until the 1V level is reached--in GaAs ICs.

"Moreover, GaAs transistors will surpass even their present record-breaking performance if built as heterojunction devices. Completely new VLSI concepts will then be implemented, like chips with RF receiver and transmitter front-ends, realized with no greater process complexity. Imagine an all-digital radio in which the RF signal is converted directly into digital signals and all of the subsequent signal processing is digital. The upshot could be truly inexpensive transmitter/receivers."

Last week, he backed off somewhat from that optimistic vision however, saying that it will be several years before heterojunction GaAs transistors are implemented. "Heterojunction is definitely not mainstream at this point. The focus on GaAs is to get it mainstream. The reason heterojunction (GaAs) VLSI is not mainstream is there is no way to do it real cheaply." He added that "We will probably see heterojunction GaAs within 5 years."

Meanwhile, H-GaAs IV power dissipation is said by Vitesse to be below 0.1 microwatt/MHz/gate at clock frequencies above 600MHz. H-GaAs IV supports supply voltages from 1.2 volts to 3.3V with less than 20 percent change in gate speed. Clock frequencies on VLSI designs up to 200,000 gates using direct-coupled-FET-logic (DCFL) can exceed 800MHz. For MSI circuits, using source-coupled-FET-logic (SCFL), 10GHz clock rates can be obtained for broadband telecom applications. Both DCFL and SCFL designs may be integrated on the same die for applications requiring both.