LSI to introduce 0.25 micron ASICs

Electronic News, Sept 18, 1995 by Jim DeTar

Milpitas, Calif.--LSI Logic will this week push the gate array manufacturing process envelope with the introduction of a 0.25 micron process, dubbed G10, which will enable design of application-specific integrated circuits (ASICs) with up to 5 million usable gates and 49 million transistors. In addition, G10 ASICs will be offered with a variety of features including new library elements and package options in an effort, LSI said, to offer a more complete application-specific solution from process to silicon.

G10 also represents a fundamental shift in the way the company does business--away from its traditional computer market base and toward consumer and communications applications. 1994 revenues were 60 percent from computer systems, 10 percent from consumer and 20 percent from communications. Company officials estimate 1995 revenues will be 20 percent or more from consumer products, about 33 percent from communications systems and the remainder from computers. As a result, although LSI has historically been known as a gate array company, the balance of power has shifted to cell-based products.

"This is a new direction for ASICs," said Jordan Selburn, LSI's product manager, ASIC product marketing. "We take everything from the process up and tune it for specific applications."

The 3.3-volt G10 series, so-named because it is the 10th generation process the company has developed, is already being used in designs with several OEMs who had early access to the process, and is expected to be available for general design use by the end of the year. Customer design actually started back in August and LSI will now promote its new technology through demo systems set up at the LSI Logic design centers.

"We have characterized three test chips and another two are in the works. The process will be completely qualified before the end of the year," Mr. Selburn said.

The G10 process is another step on the road to system-on-a-chip as designers attempt to collapse entire systems onto single-chip implementations. However, the variety of existing applications makes it difficult for a single product to serve all applications equally well.

The G10 ASIC product generation was designed to respond to this range of needs and provides the necessary adaptability through specialized technical features, libraries, tools and LSI Logic's CoreWare portfolio, according to Brian Halla, LSI's executive vice president of LSI Logic Products.

"The G10 product generation carries this revolutionary applications-optimized focus to every facet of the ASIC product, starting with silicon process, continuing through product architecture, design methodology and packaging solutions, and culminating with the rich CoreWare library of predesigned system building blocks," Mr. Halla said. Among the process innovations are a new five-layer metal option that will be offered with G10; LSI is currently rolling out its four-layer metal process.

The company is also offering a 2.5V option for low power applications. LSI's Mr. Selburn admitted OEMs will take a performance hit with the turned-down power but he contended it is not a significant one. "Often when you dial down the voltage from 3.3V to 2.5V you lose up to one-half of the speed. LSI will come in with 10 to 15 percent (loss) from the 3.3V," he said.

G10 employs what LSI terms a recessed LOCOS (LOCal Oxidation of Silicon) well isolation structure starting from low-cost P-type bulk silicon wafers. This cost-effective etch and oxide growth process provides a deep--and claimed more effective--isolation barrier between P-type and N-type well regions than a common oxide isolation, according to LSI.

The ASIC devices will incorporate a number of technical innovations including complex library elements such as three-transistor memory structures and high-performance mixed-signal functions such as 12-bit A/D and D/A converters and 270MHz video DACs (digital-to-analog converters). Although competitors such as Hitachi offer 0.25 micron ASIC process, LSI's purported 5 million usable gate count is thought to be an industry high. In addition to Hitachi, IBM earlier this year also announced it will ship products on 0.25 micron process, LSI said.

Among the markets the company hopes to make inroads on are the high-end telecommunications, engineering workstation and network server applications. These need fast gate speeds together with high I/O capability. The G10 product family features gate delays as low as 50 picoseconds and gigabit-per-second low-voltage differential signal (LVDS) I/Os and 622M/sec differential PECL.

In addition, the new ASIC technology offers cores such as MPEG-2 video decoders/encoders, 32- and 64-bit superscalar RISC microprocessors such as Digital's Alpha and the SPARC core, switched Ethernet, fibre channel and high-speed serial link communications controllers using the CoreWare design methodology for designing systems-on-a-chip.

Packaging options supporting the G10 series include high pin count flip-chips, three separate ball grid array (BGA) lines in a variety of pin counts and thermal and electrical options, thermally-enhanced PQFPs and a modeling and analysis capability for any die-package pair.