Sub-0.4-micron ASIC march goes on

Electronic News, Oct 23, 1995 by Jim DeTar

Mountain View, Calif.--The ASIC market continues its migration to sub-0.4-micron geometries as both NEC and Toshiba unveil new ASIC families. These follow closely on the heels of LSI Logic's recent announcement of its G10 line, based on 0.35-micron drawn (0.25-micron L-effective) technology (EN, Sept. 18).

NEC Electronics unveiled the CB-C9 family, its first family of 0.35-micron (0.27-micron effective) ASICs, based on the company's recently-introduced CMOS-9 architecture (EN, Jan. 30 ), which has until now been used on NEC's gate array products only. Separately, Toshiba will go its competitors one step better by unveiling a system-level ASIC line called the TC220 series using what it says is 0.3-micron drawn gate length CMOS technology.

Toshiba's TC220 series is said by the company to provide designers with 3 million gates coupled with 111 picoseconds (ps) fully-loaded 2 input NAND gate performance (41ps basic gate). Frank Ramsay, Toshiba's director of technical marketing, systems integrated circuit division, said the TC220 series is designed "exclusively for the high end market where density is critical to survival."

Mr. Ramsay noted that the new ASICs are built using Toshiba's 64-megabit DRAM process technology and also provide high density embedded SRAM. He hinted at future developments in the memory area, saying that Toshiba plans to announce very high density embedded DRAM within the next few months. In addition, the company plans to announce developments in advanced applications areas, such as signal processing, in the next six months.

The TC220 series employs 0.3-micron drawn process, in double and triple layer metal, and operates at 3.3V with a 2.5V core option available. It features a maximum raw gate count of 3 million gates with a usable gate count of 1.9 million gates on a die measuring 17.5mm x 17.5mm.

A 2.6X density increase over Toshiba's previous generation was achieved, the company said, by using a 0.3-micron drawn transistor structure along with a combination of metalization technologies including borderless contacts, vias and self-aligning contacts.

TC220 cores include a MIPS R3900 embedded processor, 8/16-bit CISC embedded controllers, high density DRAM, MPEG and asynchronous transfer mode (ATM). The next generation of the R3900 is expected to be more cost-effective on the TC220, Toshiba said.

I/O performance on the TC220 currently includes options such as LVDS, Peripheral Component Interconnect (PCI), GTL and Rambus ASIC master and slave controllers. To round out system performance, analog PLLs are also available. Typical gate delay has been minimized using optimal basic cell structure. For a variety of applications, three variations of macrocells are available.

The first, which Toshiba calls "Normal" gate strength offers basic gate performance as low as 69ps and power dissipation of 1.42 milliwatt/MHz/gate. The "High Drive" variation features basic gate performance of 49ps and power draw of 1.86mW/MHz/gate. A "High Power Drive" macrocell is said to enable basic gate performance of 41ps and power dissipation of 2.73mW/MHz/gate.

The TC220 family is slated for November availability with prototypes available in 1Q96 and production volumes expected in 3Q96. Packaging options will include 62mm inner lead TAB bonding on QFP and BGA, as well as plastic, EE and thermally enhanced versions as well. Pricing is not available, the company said.

Meanwhile, the NEC CMOS-9 process technology used in the CB-C9 ASIC family has previously been used in more than 15 gate array designs which are in production; prototypes were created starting back in June. The CB-C9 ASIC line is targeted for high-end designs such as engineering workstations, mobile communications and super computers.

Macros are currently in development to enable the CB-C9 to interface with high-speed Rambus dynamic access memory (RDRAM), integrate reduced instruction-set computer (RISC) or 16-bit 80286-compatible CPUs and allow analog/digital and digital/analog (A/D, D/A) interface conversion on the chip.

"The CB-C9 family supports NEC's OpenCAD design system which allows designers to mix and match tools from a variety of electronic design automation vendors," said Toru Kamisaki, NEC's strategic marketing manager for workstation applications. "The OpenCAD system aids designers in the development of complex multimedia equipment, personal digital assistants (PDAs) and set-top boxes."

This latest family operates at 3.3 volts and utilizes NEC's three-layer metal CMOS process. The CB-C9 family offers 25 sizes ranging from 80,000 to 3.5 million raw gates (56,000 to 1.6 million usable gates). Performance is listed as 113ps for a 2 NAND gate loaded with two fan-outs and 0.4-millimeters of wire, enabling the devices to support target system speeds of up to 150MHz.

Providing a roadmap to future versions, NEC said it plans to support 2.5V and 2.0V standards found in sixth and seventh generation CPUs. Future library updates will include support for high speed I/O such as high speed transceiver logic (HSTL), Gunning transceiver logic (GTL) and pseudo-emitter coupled logic (pECL).