High Level unveils floorplanner

Electronic News, Feb 19, 1996

Santa Clara, Calif.--High Level Design Systems (HLDS) announced Top-Down DP, a floorplanner combining production-proven floorplanning techniques with hardware description language (HDL) estimation and analysis technology to give IC designers accurate predictions of chip-level performance characteristics like size, timing and power consumption for deep-submicron designs.

Focused at the register transfer level (RTL), Top-Down DP reduces design cycle times by uncovering and fixing major design problems associated with the physical implementation of a design at the HDL entry phase, the most cost-effective fix time.

The product reads and analyzes HDL code to generate estimates for size, timing and power while automatically creating a chip-level floorplan allowing designers direct access to deep submicron physical implementation information like top-level interconnect parasitics crucial to accurate prediction of chip-level performance characteristics.

Introducing physical reality to the HDL design phase allows Top-Down DP to reduce the number of iterations between RTL design and the synthesis step to the place-and-route step, reducing design cycle time and time to market.

"Performance, power dissipation and chip size problems often must be fixed by making architecture, partitioning, or major design changes," said Bob Wiederhold, HLDS' executive VP and COO. "Since fixing the problems can require fundamental changes to the HDL description, a designer would ideally like to catch these problems before spending a lot of time synthesizing to the logic level and implementing the design physically."

Using only an RTL source-level design description in Verilog HDL, Top-Down DP allows quick gate number and area estimations for each RTL process and module, creates a floorplan for the design and analyzes the chip's size, performance and power dissipation. Since it operates at the HDL level, crucial architecture, partitioning and design decisions can be made before synthesizing and floorplanning at the logic level, allowing better design data and constraints to be passed to synthesis and physical implementation tools.

At the product's heart is the HDL estimator, which reads in pre-synthesized Verilog HDL and produces an HDL graph-based data model for use by other TDP analysis tools. Estimation is based on a high speed proprietary compiler technology and a HDL source code annotator tool in TDP allows a designer to see the source annotated with size information and numbers of latches, registers and multiplexers in the form of Verilog comments.

Chip-level timing is analyzed by processing the proprietary graph-based data model. "RTL size and timing estimation creates a unique set of issues," said George Janac, HLDS' VP of engineering. "If you estimate the size of circuit for functionality you have one set of results. When you specify timing goals, size of a circuit must be adjusted to meet those goals, making size and timing interdependent. The key to RTL analysis is to be able to quickly identify unfeasible timing paths and provide realistic feedbacks to the HLD designers."

Directly from the HDL source, Top-Down DP creates black-box timing models which can then be combined with wire and floorplan information to perform full chip timing simulation. It interfaces directly to Synopsys' Design Compiler and is listed at $65,000, with 2Q96 availability.