LSI merges EDA tools in new product

Electronic News, Feb 26, 1996 by Judy Erkanat

Milpitas, Calif.--In cooperation with the industry's leading electronic design automation (EDA) tool suppliers, LSI Logic will soon deliver toolkit methodology guaranteeing deep-submicron system-on-a-chip performance. The company announced its blending of popular EDA tools into its integrated, standards-based ToolKit design environment.

During the past three years, LSI formed long-term alliances with EDA vendors to create a deep-submicron silicon design environment allowing multi-vendor tools to cooperate with the ToolKit environment to share and exchange design data.

Standard interfaces enable cooperation of EDA vendor tools within LSI's manufacturing/design environment. Standard interfaces include VHDL, Verilog, SDF, PDEF and WGL. LSI complies fully with the IEEE Vital-95 library standard for VHDL.

"By providing an integrated environment to support our ASIC design flow and to verify system building block cores, memories, mixed-signal functions, and macrocells, the LSI Logic ToolKit is the foundation of our CoreWare methodology and multi-million-gate, submicron ASIC designs," said Brian Halla, LSI's executive VP of products. "We see our customers standardizing on several best-of-class EDA tools from select vendors. We support our customers' choices by coupling our system-on-a-chip expertise with these best-of-class EDA tools."

LSI's design and modeling methodology, plus silicon-specific delay prediction, fuel multi-vendor EDA tools to accelerate the production of fully functional sub-micron silicon chips. With close cooperation from Cadence Design Systems, Mentor Graphics, Synopsys, Viewlogic Systems and others, LSI created the ToolKit design environment for predictable design, rapid sign-off and thorough manufacturing test.

"Since we signed our alliance with LSI Logic in 1993, Synopsys has worked closely with LSI Logic in a joint methodology development effort to meet modeling and layout integration requirements for synthesis and verification and sign-off of large submicron designs," said Aart de Geus, Synopsys' CEO. "This has resulted in tremendous success for our mutual end-customers. We're excited that ToolKit brings together full support for high level design including synthesis, simulation, and test using Synopsys products such as Design Compiler, VSS (VHDL System Simulator) and Test Compiler."

Mentor's president and CEO, Walden C. Rhines, agreed. "Mentor Graphics has enjoyed an ongoing relationship with LSI Logic to deliver systems on silicon solutions to our mutual customers," he said. "We are pleased that LSI Logic's new ToolKit system incorporates sign-off support for Mentor Graphics' FastScan automatic test pattern generation (ATPG) tool, and QuickHDL, the Mentor Graphics/Model Technology Vital-95 compliant simulator."

Strong multi-year alliances with major EDA vendors is the key to the success of LSI's ToolKit sign-off system. Tools, libraries, and methodology are fine-tuned through close cooperation and continual standardization efforts.

"As the initiator of both Verilog and Vital standardization efforts, Cadence is delighted to see the recent IEEE endorsements and rapid industry acceptance of these popular standards," said Tony Zingale, senior VP of marketing at Cadence. "We worked very closely with LSI Logic to develop sign-off quality verification flows and libraries for Cadence's Verilog-XL and Leapfrog (VHDL) simulators. With LSI Logic's support of both Verilog and the Vital-95 standards, our mutual ASIC design customers now can design with the HDL of their choice while being guaranteed to have working silicon the first time."

In its initial release, the LSI ToolKit environment will provide full synthesis support using Synopsys' Design Compiler. Verilog sign-off can now be performed using these EDA vendor tools; Cadence Verilog-XL simulator, Chronologic VCS simulator, Quad Motive static timing analysis tool and the Mentor FastScan tool for ATPG/full-scan insertion.

LSI ToolKit's Vital-95 beta support will begin shipping in March with full simulation sign-off available early in the second quarter of 1996. Planned Vital-95 compliant simulators include Cadence Leapfrog, Mentor QuickHDL, Synopsys VSS and Vantage Optium.

Sign-off, batch-oriented tools are available on multiple workstation platforms, including Sun Microsystems, Hewlett-Packard, Silicon Graphics, IBM and Digital Equipment Alpha series.

"Time-to-volume has become the marching orders of this decade," said Will Herman, Viewlogic's president. "LSI Logic has clearly led the pace in advancing the verification methodology. The cooperation effort between LSI Logic and Viewlogic has been a driving force in the inclusion of our leading Verilog simulator (VCS) and Motive as sign-off tools within their ToolKit methodology.

"Not only does the move to static timing-based sign-off improve the quality of designs, but it also has a major positive impact on time-to-volume. We are also pleased with their efforts towards inclusion of our Vantage Optium for high performance VHDL-Vital-95 compliant simulator. Our relationship with LSI Logic will provide our mutual customers with comprehensive solutions well into the 21st century."