VLSI, PMC-Sierra add network chips

Electronic News, March 25, 1996 by Crista Hardie

San Jose, Calif. and Vancouver, B.C.--VLSI Technology and PMC-Sierra are adding to their high-speed network offerings with multi-port transceiver devices scheduled for 2Q96 release.

In the drive to incorporate more functionality into smaller spaces, VLSI is bringing out a single-chip four-channel user network interface (UNI) for local area network (LAN) and wide area network (WAN) asynchronous transfer mode (ATM) backbones, while in the T1/E1 arena, PMC-Sierra is introducing a pair of four-channel devices for public and private network applications.

VLSI will today unveil the VNS67200 ATM Quad UNI, a single chip supporting four full-duplex ATM channels. Each port can be independently configured to handle ATM traffic at 25 megabits-per-second, 52M/ps or 155M/ps.

The company plans to demonstrate the device at the NetWorld trade show in Las Vegas in April. Meanwhile, select VLSI customers are already sampling VNS67200 prototypes. General samples are expected to be available in April, with volume production in the summer. Per-unit price in 10,000-unit quantities is $75. The 5-volt device is packaged in a thermal MQFP package.

Designed primarily for system level backbone or edge node equipment, the quad UNI is likely to find initial applications in LAN hubs providing an ATM connection to the desktop, or in ATM switches, said Craig O'Sullivan, product manager for the ATM Quad UNI. Closer to the desktop, the device can be used in video or multimedia file servers that need multiple connections into a high-performance backbone, he added.

The ATM Forum Utopia Level 2 bus interface standard allows up to 32-ports to share a single bus, which means that up to eight quad UNIs--or multiple quad UNIs in combination with other UNI-compliant devices--can be connected to the same bus.

"This is the first of several products with multi-PHY capabilities we will bring into this marketplace," Mr. O'Sullivan said. "We will be listening to customers and including the features most in request in the marketplace." Quad channel devices are likely to evolve into six or eight channel devices, or clock/recovery functions might be integrated in future generations of the chip, he suggested.

Meanwhile, PMC-Sierra is rolling out two single-chip additions to its T1/E1 product family--the PM4314 QDSX quad T1/E1 Line Interface Unit (LIU) and the PM6344 EQUAD quad E1 framer. The devices are designed for high-density switching applications like ATM and synchronous optical network/synchronous digital hierarchy (SONET/SDH) where LIU and framing functions need to be physically separate, such as in digital access cross-connect switches.

The QDSX is available in sample quantities now; volume pricing will be $32 each. The EQUAD is expected to sample in 2Q96, priced at $59 each in volume quantities. Both devices are packaged in rectangular 128-pin PQFP packs.

"The increased silicon integration provided by the QDSX and EQUAD offer an overall reduction in system cost for the designer. This is paramount for markets such as T1 and E1, where the applications are established and extremely cost sensitive," said Steve Perna, VP of marketing and business development at PMC-Sierra.

The EQUAD integrates four E1 framers on a single chip. The QDSX LIU interfaces directly to the EQUAD or to an equivalent T1 framer or quad E1/T1 multi-PHY ATM UNI for a four-channel transceiver solution. When used with compatible software drivers, the chips can provide a single design for both E1 and T1 applications, PMC said.