Sun intros heat RISC arena

Electronic News, April 8, 1996 by Jim DeTar

Mountain View, Calif.--Activity heated up in the RISC market last week as Sun Microsystems unveiled a new workstation version of its Sparc architecture and separately introduced an embedded version--microSparc-IIep--at the Embedded Systems Conference in Boston. MicroSparc-IIep will be the first Sparc microprocessor to incorporate the Peripheral Component Interconnect (PCI) bus controller.

Sun also revealed software tools and computer systems partnerships with more than 20 companies supporting UltraSparc, a strategic move designed to position Sparc to compete with a variety of very active RISC competitors, including the IBM/Motorola alliance, which last fall took the wraps off of a common hardware platform at Comdex (EN, Nov. 20, 1995), as well as Advanced RISC Machines (ARM), Hewlett-Packard and others.

ARM last week revealed its network computer (NC) roadmap for development of processors for Oracle's planned line of inexpensive Internet connect devices, and at the same time also announced support for the ARM microprocessor by a variety of software vendors (story on page 64). And Hewlett-Packard last week announced new performance benchmarks for its HP-RISC architecture PA-8000, with a claimed SPECint95 performance benchmark of 11.8 (compared with 5.6 for the first-generation 167MHz UltraSparc) and SPECfp95 of 20.2 (compared with 9.1 for the UltraSparc).

Meanwhile, Sun took the wraps off of the first in a new family of embedded Sparc MPUs. The family will consist of general-purpose MPUs targeted specifically for embedded applications, including office automation, telecommunications and intra-networking.

The 3.3-volt microSparc-IIep, the first member of the family, with a target price of $700 will offer an initial claimed performance of 125 MIPS at 100MHz and will be the first Sparc to offer an on-chip Peripheral Component Interconnect (PCI) bus controller.

Dhaval Ajmera, marketing director for Sun Microelectronics' Embedded Products Group, noting the increasing acceptance of the Intel-developed bus said "Based on strong market demand, we're adopting PCI--the popular bus standard--on Sparc embedded processors." The microSparc-IIep is slated to sample in 4Q96.

S. K. Vinod, embedded Sparc product marketing manager, said because the embedded microSparc-IIep is compliant to the Sparc V8 architecture, systems developers can use code tested on Sparc-based workstation without the need for cross-compilation. Developers working with legacy Sparc designs can now move quickly to PCI bus-based designs.

"By developing and deploying on the same architecture, designers avoid the problems associated with the classic routine of developing on the host platform, cross-compiling to the target microprocessor, setting up the emulator and debugging," Mr. Vinod said.

The processor also features a high-speed direct memory interface and flash PROM interface providing high performance for networked embedded applications. An on-chip, 32-bit flash PROM interface allows direct connections to flash devices and enables real-time operating systems and applications to boot and execute from ROM. The PROM interface is suitable for the diskless systems typical in small, deeply embedded applications.

The direct memory interface is said by the company to increase memory bandwidth by allowing data transfers to take place without blocking the processor. The DRAM memory interface controller generates all of the signals needed to support up to 256 megabytes of system memory, with a 64-bit wide data bus and support for EDO DRAMs. The on-chip refresh controller is programmable, and self-refreshed DRAMs are also supported.

In the desktop arena, Sun's Microelectronics division VP of engineering Anant Agrawal said the company has achieved first silicon on its second-generation UltraSparc-II. In about a year since the UltraSparc was introduced, Sun's engineering team has doubled the clock speed of the 5-million-transistor UltraSparc MPU to 300MHz.

Mr. Agrawal said the UltraSparc line has come in on schedule. "UltraSparc-I arrived on time and exceeded the performance estimates we communicated in the roadmap. Now, with UltraSparc-II, we are running like a well-oiled machine. We will sample UltraSparc-II this quarter and expect production availability in 3Q of this year."

In terms of performance, the company said UltraSparc-II silicon boots multi-user Unix at clock rates up to 300MHz and Sun estimates that the first family members will have SPECint95 values in the range of 8.5 to 11 and SPECfp95 values from 15 to 18 (with 2-megabyte cache).

Microarchitectural changes have been made to UltraSparc-II for reduced instruction cycle time, including the addition of full software prefetch and the ability to handle multiple outstanding requests. Second-level cache support has also been extended to 16MB and flexible system clocking and cache interference schemes have been added to UltraSparc-II.

UltraSparc-II features what the company terms the New Media VIS (Visual Instruction Set) which scales system bandwidth to 3 giga-operations/second (GOPs) and 1.6 gigabyte/second (GByte/s).