Philips making its bid into high density PLDs

Electronic News, April 8, 1996 by Jim DeTar

Albuquerque, New Mexico--The high-density programmable logic market is about to get a bit more crowded as Philips Semiconductors will today unveil a family of complex programmable logic devices (CPLDs) called the CoolRunner line. As reported earlier (EN, April 1), the company will also reveal the formation of a new business group called the CPLD business unit.

Philips, which has offered simple PLDs (SPLDs) since 1974, will use its patent-pending XPLA (eXtended Programmable Logic Array) architecture in its first CPLDs. Another pending patent covers a power management design technique dubbed Fast Zero Power (FZP). Philips will use both EEPROM and SRAM technologies--starting with EEPROM.

Several large, general purpose semiconductor companies including Intel and Texas Instruments have in recent years sold off their PLD businesses, while others such as Philips and competitor Advanced Micro Devices (AMD) are betting that--although currently dominated by independents--the market still has room for larger semiconductor houses. AMD recently formed a wholly-owned subsidiary to focus on that market (EN, March 18).

The idea of the behemoths expanding in the PLD market may not be as radical an idea as some might think. According to market research firm Pace Technologies, AMD was the market leader in 1995 for simple CMOS PLDs and number two for CPLDs behind Altera. Although posting lower than overall PLD market growth, AMD had a healthy 58 percent gain in sales during 1995 to $324.3 million for the year.

Today, Philips Semiconductors has total PLD sales of less than $50 million, but the company has what it calls a conservative goal to reach a target of $110 million in CPLD sales alone by 1999.

Philips Semiconductors, which posted sales of $4 billion last year, a tenth of Philips Electronics $40 billion in revenues, has the resources to back its venture and will initially put $30 million of seed money into the unit.

The Philips CPLD business unit, to be located here, will initially focus on three market segments: the 3.3V high-performance market where high speeds are necessary to improve overall system performance, any power sensitive applications including notebooks, telecommunications equipment and handheld instruments; and the mainstream 3.3V and 5V markets.

Steve Kelley, GM of the company's programmable logic group, and Mark Aaldering, applications manager for the group, outlined the company's strategy.

Mr. Kelley said "We hope to dominate the 3-volt market and the portable segment of the 5V market. We are trying to dominate the power-sensitive." He was quick to add though that Philips will at first concentrate on its niche and not take on the market leaders. "We are not trying to put Altera out of business." And, unlike AMD, Philips has no plans to form a separate PLD company, he said.

Mr. Aaldering said the company's first family will have between 1,000 and 4,000 gates. Philips' XPLA architecture will combine PALs (programmable array logic) devices and PLAs (programmable logic arrays), Mr. Aaldering said. "Each macrocell has five private PAL product terms, a feature that adds flexibility." Although the die for Philips CoolRunner CPLDs will be about the same size as competitors' "It is close to being as simple as a 22V10 in terms of timing."

The CoolRunner CPLDs will feature propagation delay for PALs of 6 nanoseconds at 5V and 8ns delays at 3.3V. With PAL and PLA cells together, the tPD goes up to a modest 8ns. The devices will initially be manufactured on 0.5-micron process, later to go to 0.35-micron, and will be packaged in 120-pin PLCC packages.

Philips said it has seen first silicon with its CPLDs and will shortly introduce a 32-macrocell product, initially in 120-pin PLCC packaging. In addition, the company is partnering with Minc and Synario for advanced tools and will offer a stand-alone tool for $95 that is PC/Windows-based and includes Boolean entry, simulation, static timing analysis and device compilation.