Fabless firms in transition; Cyrix, Cadence pact: breaking new ground

Electronic News, April 22, 1996 by Jim DeTar, Judy Erkanat

Richardson, Texas--Cyrix signed a multi-million-dollar agreement with Cadence Design Systems under which Cadence will assist Cyrix in the development of the company's seventh-generation microprocessor family, code-named M3. One significant aspect of the agreement is the planned application of Cadence's as-yet-unreleased advanced logic verification technology, code-named Cobra.

Competitor Intel was quick to note that there are potential pitfalls in the partnership--specifically in that Cadence's compensation is dependent upon achieving several tangible milestones during the development process, culminating with the delivery of 10,000 chips. This potentially puts Cadence in a vulnerable position if the market fails to readily accept Cyrix' M3.

Sources at Cyrix said the M3, which will have a Cyrix M1 core at its heart, will incorporate more than 10 million transistors. Given the complexity of the device, Cyrix decided to use unconventional methodology for advanced verification and other tools-related functions.

This relationship represents a radical departure from the usual silicon vendor/tools vendor relationship in that silicon vendors such as Intel and Advanced Micro Devices generally use off-the-shelf tools for verification. Cadence said this is, in fact, the first time that it has partnered this closely with a microprocessor company.

The agreement stipulates Cadence's compensation be dependent on achieving several milestones during the development process of Cyrix' next-generation microprocessor product family, culminating with the delivery of 10,000 chips.

The deal also calls for Cadence to maintain an on-site program manager at Cyrix, and a senior member of Cadence's engineering team to serve as technical lead on the project. The joint engineering teams will work together throughout the design process of Cyrix' seventh-generation microprocessor, a unique model for a vendor-customer relationship.

Another agreement provision is the application of Cadence's as-yet-unreleased advanced logic verification technology, including its cycle-based simulation and formal verification software, as well as IC place-and-route technology and services aimed at Cyrix' deep-submicron silicon processes.

The agreement is custom-tailored for Cyrix, which is a fabless semiconductor company relying on a variety of outside partners including manufacturing partner IBM. Much smaller in size and unable to compete in terms of sheer engineering strength with primary x86 MPU competitors Intel and AMD, Cyrix has chosen to use Cadence. Cyrix was quick to note, however, that it will continue to do a significant portion of its own CAD work in-house.

Kevin McDonough, the Cyrix senior VP of engineering who signed the contract with Cadence, characterized the agreement as one which extends the company's fabless semiconductor model and one which will allow Cyrix to allocate precious design resources elsewhere.

"Tapping into the expertise of a world-class development team like Cadence makes strategic sense, allowing us to focus our resources, for instance on compatibility tools--a key Cyrix strength," Mr. McDonough said. "The bottom line: Cadence proved to be very forward-thinking in structuring a relationship where they put some skin in the game so both companies are motivated to meet our development goals."

Joseph Costello, Cadence's president and CEO, said the relationship will benefit Cadence by enabling it to segue into faster product development arenas, specifically the advanced microprocessor development market.

"Product developers such as Cyrix which are pushing the leading edge need more than just advanced design automation technology to be successful," Mr. Costello said. "Our goal is to provide Cyrix with a complete solution to their business objective of delivering state-of-the-art microprocessors on time, to spec. To do that, we need a creative, flexible approach to working with them, which includes a multi-functional team of Cadence people working on site at Cyrix and the most sophisticated technology in our portfolio."

Patrick Scaglia, Cadence's VP of engineering and the director of Cadence Berkeley Labs (CBL), told Electronic News the joint project is already under way. Mr. Scaglia also fleshed out Cadence's unreleased logic verification technology.

"The internal project name for the cycle-based simulation is Cobra," said Mr. Scaglia. "The formal verification is a generic technology and we have been working on both at CBL. With Cyrix, we are delivering very advanced technology on a custom basis."

In a joint interview, Paul Kollaritsch, Cyrix design automation manager, and Mike Shebanow, product manager for Cyrix' seventh-generation processor development, outlined the strategy behind the move. Mr. Kollaritsch touched on the perceived benefits for both Cyrix and Cadence.

"We get early access to new tools coming down the line and close cooperation with Cadence R&D guys," Mr. Kollaritsch said. "We will go through the many iterations it takes to get a fine, 'bleeding-edge' tool customized--as opposed to out-of-the-box, shrink-wrapped tools." Cadence, although it is Cyrix' closest partner, is not Cyrix' only software tools partner. Among the other tools Cyrix is using are Meta-Software's HSpice and Synopsys' logic synthesis tools.