TI sets 0.18-micron move into next ASIC frontier

Electronic News, May 27, 1996 by Peter Brown

Dallas--In a bid to cross into the next generation of ASIC technology, Texas Instruments introduced what it calls its Timeline Technology for building semiconductors with 0.18-micron linewidths and 125 million transistors on a chip.

Timeline Technology features system-on-a-chip integration designed to enable OEMs to customize their cores with such features as digital signal processors (DSP), microcontrollers, DRAM, SRAM, flash memory, ROM and other high-level functionality. Each device is said to have up to 20 million "raw" gates; TI didn't say how many usable gates there are in that total.

"Texas Instruments' announcement of its 0.18-micron technology has served notice to the rest of the industry that they are a serious leading-edge supplier," said Jerry Worchel, In-Stat senior analyst.

There are few products in the semiconductor industry these days that are without a DSP chip in them, according to Dave Shepard, TI's worldwide DSP solutions marketing director. However, there are very few products with multi-DSP chips in them, which Timeline Technology enables.

"Customers say if a company can integrate onto a single chip all the functions they need, then a major problem is solved right from the onset," Mr. Shepard added. According to TI, designers will be able to select from multi-DSP or microprocessor cores and surround them with other specific modules without exceeding the transistor capacity. This eliminates having to coordinate with different vendors to achieve the best product--the whole system can now come from one source.

Rich Templeton, TI senior VP and worldwide manager of its ASIC business, said the time-to-market advantage allows engineers to drop larger quantities of circuitry into a design, rather than starting from scratch. "To create the tightest, most elegant solution may take a year or more. But with all of the capabilities that our Timeline technology provides, the design cycle drops to a few months," Mr. Templeton added.

Having 125 million transistors on one piece of silicon opens the doors to powerful new processors, TI said. It allows for multiple processors on one chip instead of one or two. Michael Hames, TI Semiconductor Group VP and worldwide DSP manager, said: "What you would find is that, rather than compromising to build processors capable of multiple tasks, you would have a sequence or series of processors, each of which does one thing very well."

Mr. Shepard said TI believes there are two markets for lowest power applications: highest performance, consisting of speed driving applications such as telecommunications and workstations; and highest density, consisting of hard disks, wireless communications and auto/visual systems. "We think we will be able to hit both ends of this low-power market with the new technology," Mr. Shepard said.

The Timeline technology will be available for beta testing in 2H96 and is slated to be in volume production in 1H97.

Earlier this month, IBM unveiled its 0.18-micron ASIC, the SA-12, which IBM says can be used to create ASICs with up to 3.2 million gates (EN, May 13). Production on IBM's ASIC will begin in 1997 as well.

TI currently is building a $2 billion megafab for the Timeline ASIC products in Dallas, slated for opening sometime next year. The technology will come in PLCC, TQFP and plastic ball grid array (BGA) packaging.