Million-gate ASICs pose challenge

Electronic News, June 10, 1996 by Jim DeTar

Mountain View--A new paradigm is emerging in the application specific integrated circuit (ASIC) industry as it surges past the million-gate mark, and--according to some industry observers--returns to a previously-abandoned semiconductor design model. This return to what is termed a "neo-classic" ASIC design model is driven by the movement of ASIC houses to integrate more complex cores, according to Jeff Lewis, VP of marketing at Compass Design Automation.

However, some in the industry are saying that a ceiling has been reached and ASIC companies will not get past the million-gate ceiling because it's not economically feasible to build such devices.

Compass Design's Mr. Lewis said that the ASIC industry is experiencing intense change which will lead to a new paradigm. "What we're seeing now is what is being called a variety of things including the deconstruction of the ASIC industry where you actually have a disintegration of vertical suppliers like the ASIC vendor and actually you're getting niche suppliers providing all the different pieces of this design flow. And that's what I'm calling the neo-classical semiconductor flow."

Mr. Lewis asserted that everyone is becoming a semiconductor designer again as a result of the increasing use of pre-designed cores in ASICs.

However, some semiconductor industry figures take it a step further, saying the ASIC business is not only in turmoil but it has hit a ceiling at a million gates--that is simply not economically feasible to build them.

Naeen Zafar, VP of marketing at gate array conversion house Quickturn Design Systems in Mountain View, is one of those who believes that the million-gate-plus ASIC may be too expensive. Mr. Zafar said "I believe a million-gate ASIC is a dying breed. And some people hold the view that further down (the road), due to the economics of this thing it simply will not be economically feasible for many of us to do that."

Mr. Zafar asserted what will emerge are companies that will develop very complex ASSPs (application specific standard products). He cited the names of some of these companies: "Companies like Chromatic, companies like NVidia, companies like 3Dfx--just specialty small houses which will have very complex, highly integrated standard products. And most of the ASICs will be small."

Mr. Zafar's belief that the ASIC business has hit a ceiling is challenged however by others in the industry.

Jean-Louis Bories, VP of LSI Logic's ASIC Milpitas division, commented "Every time you generate a new technology it is integrated. One-million or 2-million gate technology, the customer will always push this technology to the limit."

In addition to the economic challenges, other obstacles to million-plus gate designs are emerging that may prove formidable for even veteran gate array vendors such as LSI Logic, Toshiba and IBM.

Ann Marie Rincon, IBM senior engineer, ASIC methodology and architecture, cited a couple of potential show-stoppers.

"Design verification versus turnaround time is a major issue. And when you are trying to get a functional timing and testability verification all in one tool, I think that's become a problem and a barrier to 1 million gate ASICs.

"Consistent timing data--I really think that this is going to be key to making 1-million gate ASICs and into the 2 and 3-million gate ASICs.