More layers spur polishing

Electronic News, July 15, 1996 by Gale Bradley

San Francisco--As layers of metal on high-end ICs increase, with four layers the industry average and six-layer processes in production at Intel, semiconductor equipment and materials suppliers are watching their business multiply and waiting for the next upsurge.

One of the most visible signs of growth in this market is the rise of chemical mechanical polishing (CMP) suppliers, like Integrated Process Equipment Corp. (IPEC), R. Howard Strasbaugh, Ebara of Japan and Speedfam. And with memory devices just wading into multi-layer metal (MLM) technology, eyes are peeled to see if memory manufacturers, particularly Asian suppliers, adopt CMP or not.

"The big question--it's kind of a heated debate--is whether the DRAM manufacturers are going to use CMP or not. It's not a given...Widespread use of CMP for memory could come at 64 (megabit), but more likely at 256," said Laura Peters, an analyst with Integrated Circuit Engineering (ICE).

"The reason there is so much question is it's so expensive...Some people are asking if they want to bring in an expensive process at this stage in the game," Ms. Peters said.

Dan Hutcheson, president of VLSI Research, had a similar view of the cost barrier to memory makers' adoption of CMP. "Every additional CMP step adds $7 to $10 to the cost of manufacturing the wafer. With memory, you are very cost driven, and if you can design around the process, you do. The improvement CMP provides for speed is a bigger thing in logic," he said.

"That may change as we go forward. SRAM people are going to use it before the DRAM, we know that, because SRAMs have more metal layers," Mr. Hutcheson said.

Mr. Hutcheson, though, was not discounting CMP growth. "CMP is still going to be the fastest-growing market in the entire equipment industry for the foreseeable future, which is about five years out." He added, "Some consider it still a black art; it's not really a science."

CMP competes with etchback processes, Ms. Peters said, and this is what prompted the likes of Lam Research and Tokyo Electron Ltd. (TEL) to partner with IPEC-Planar this year. Applied Materials late last year went ahead and entered the CMP tool market with their Mirra line, and enlisted OnTrak Systems for post-CMP cleaning, she said.

Mr. Hutcheson had some account for IPEC-Planar's success. "IPEC is probably the only one that is market-oriented. Speedfam has got a great machine; it's just that they haven't been able to figure out how to penetrate the market. Part of that is because when IPEC bought Westech, the two (Westech and Speedfam) weren't really competing" when they were primarily making the equipment for wafer vendors to planarize blank wafers.

"Wafer makers do a lot of hand holding with their vendors. When you make that transition into the chip industry, the chip industry expects the equipment maker to do that," Mr. Hutcheson said. "That's why it was such fertile ground for IPEC."

In the arena of equipment that lays down any of the device layers--metal or non-conducting, dielectric--some managers and industry analysts see a breakout of physical vapor deposition (PVD) versus that of chemical vapor deposition (CVD). CVD is coming along as the standard for dielectric layers, but PVD is not losing support for metal deposition.

Rich Wiley, director of corporate marketing for Materials Research Corp. (MRC), which makes both CVD and PVD equipment, said: "The CVD side is really starting to take off right now. CVD allows you to put down a barrier that's more conformal.

"Our feeling is that ultimately CVD will win out in this battle for barriers...PVD doesn't have good sidewall coverage," Mr. Wiley said. To that end, MRC has been driving their business for metal CVD of titanium and titanium nitride for a couple of years, and is developing a "global interconnect" process to bring to market.

The process, sometimes called dual damascene, can reduce by 20-30 percent the number of steps for interconnect from plug to plug. "You will be able to fill the plug and do the interconnect from plug to plug at the same time, in one deposition step," he said, and the technology calls for CMP, another reason for the CMP sector's optimistic outlook.

Ron Powell, the director of Varian Associates' research center in Palo Alto, Calif., said his company is looking at the same development: "Dual damascene is going to be a tremendous challenge. It's like filling a rain gutter and a downspout simultaneously."

But Mr. Powell was quick to point out that his company, and the other marketers of both CVD and PVD equipment, namely MRC and Applied Materials, are hedging their bets in both races. He said there is potential in ionized PVD and force fill and recognized, inherent advantages in keeping PVD around.

"Most people would like sputtered solutions. It's simple. PVD by its nature is a low temperature process, though some advanced PVD is higher. But there are no toxic gases and no impurities, because it occurs in ultra-high vacuums. It is purer than CVD and the pressure of deposition is very much lower," Mr. Powell said.