Analog IC performance: concert of process, IC designer and system needs

Electronic News, August 12, 1996 by Martin Giles

The performance of digital designs can be estimated and discussed by the use of a wide variety of "short-hand surrogate metrics" that have become quite common throughout the industry. If a digital component is characterized as high-performance CMOS using a 0.25-micron process, we immediately have a feel for where it fits within the current universe of digital ICs. Likewise, we can get a feel for a digital IC's performance by using such size and density surrogates as the number of gates or transistors that comprise its circuitry. While sometimes superficial, these commonly used metrics do provide a useful way for describing and comparing digital IC designs.

On the other hand, such simple metrics are not very useful in evaluating the performance of analog designs. While analog ICs can be described using some of the above categories, the ultimate performance implications are not so straightforward. Rarely can a single metric, such as number of gates, be attached to an analog design with any real meaning. Usually several parameters within each metric category must be considered as well as the tightly linked interdependence between the various types of metrics.

Ideally, a digital design tries to minimize the impacts of "outside-world" events in order to maximize internal performance. On the other hand, analog ICs are intended to deal with "messy" real-world phenomena such as sound, light, heat, motion and pressure. As a result, analog designs inherently must operate in challenging environments with wide variations in voltage levels, dynamic ranges, bandwidths, linearity and noise.

Ultimately, the performance of any analog design comes down to successfully orchestrating the tight interdependence between the silicon processes, the IC designer's skills and the overall system's requirements.

The process

One of the fundamental differences between digital and analog ICs is in the fabrication process. The majority of today's high-performance digital designs use CMOS, or an equivalent process, driving toward feature sizes below 0.5 micron, and often as small as 0.25 micron. Digital CMOS circuit design is basically a surface-oriented process that lends itself to two-dimensional characterizations such as feature sizes. Overall performance is influenced primarily by how finely you can draw a feature on the surface, which drives the density of circuitry that can be included on the device.

Conversely, analog design is usually driven by use of bipolar processes which bring into play three-dimensional issues, such as diffusion depth. Effective circuit design within the vertical dimension becomes a major factor in achieving overall device performance. While this third dimension significantly complicates design complexity, it also allows achievement of higher performance at equivalent levels of surface dimension. As a result, bipolar designs can typically achieve the same speed as CMOS designs which use feature sizes that are as much as three to four times smaller. For instance, a bipolar design using a 1.0-micron process can achieve speeds equivalent to CMOS designs using a 0.3-micron process.

Using surface dimension size as a simple across-the-board metric could lead one to erroneously believe that today's 0.5-micron bipolar devices inherently deliver less performance than CMOS designs which are moving into the 0.25-micron range. In reality, a well-designed 0.5-micron bipolar device can theoretically deliver performance that is equivalent to a 0.1-micron CMOS process.

Unfortunately, while today's bipolar designs can match or exceed the performance of smaller CMOS designs, this does not mean that simply applying a factor to existing feature sizes will give us a new metric that is valid for comparing analog IC performance. The simple size-to-performance correlation that exists in the digital world cannot be applied to the three-dimensional complexity of analog design. Just because a manufacturer's process produces high-performance op-amps is not a useful indicator that it will produce a high-performance digital-to-analog converter (DAC).

Fundamental to evaluating analog device performance is understanding the role of the complementary processes being used in today's bipolar designs. As supply voltages have fallen, complementary designs, combining both NPN and PNP transistors, have become key to maintaining required dynamic ranges. Over the years, the need for complementary processes has been a major factor in fueling the trend toward CMOS. However the availability of bipolar complementary processes, for example National's VIP (Vertically Integrated PNP) process, is now helping to overcome some of the inherent limitations in integrating PNP and NPN transistors into complex bipolar devices.

In traditional bipolar design, PNP transistors have been strictly lateral devices, defined by their surface geometry, whereas NPN transistors have been vertical devices, taking advantage of diffusion depth. Prior to the advent of complementary bipolar processes, this difference has meant that overall performance of the analog device would suffer because standard PNPs had a surface base width up to an order of magnitude larger than the NPNs on the same die.