FIFO memory makers taking two paths

Electronic News, Sept 30, 1996 by Andrew MacLellan

San Jose, Calif.--In a sign that first-in first-out (FIFO) memory may be diverging into two technology paths, Cypress Semiconductor today will roll out a family of 100MHz high-density synchronous parts which advance a standard described within the industry as at the same time both cutting edge and obsolete.

Reaping the gains of its proprietary RAM3 process technology, Cypress' new DeepSync FIFO CY7C42xx family adheres to the de facto FIFO industry standard introduced in the late 1980s by Integrated Device Technology (IDT).

By remaining faithful to the standard--one which IDT has abandoned as it moved toward denser FIFOs--Cypress' new x9 and x18 parts will offer lower power, cost and latency penalties when compared against competing IDT parts using SRAM-based architecture, asserted Cypress product marketing manager for specialty memories Geoff Charubin.

The 16-kilobit x 9-bit (CY7C4261) and 32K x 9-bit (CY7C4271) DeepSync parts are available in a 32-pin PLCC and 32-pin TQFP packages for $21 and $27.30 respectively, breaking the $1-per-kilobyte threshold. The 8K x 18-bit (CY7C4255) and 16K x 8-bit (CY7C4265) ICs are packaged in both 68-pin PLCCs and 64-pin TQFPs with respective pricing of $21 and $27.30. Lot are sold in 10,000-unit quantities.

IDT said it diverted from its own standard two years ago when it introduced the high-density SuperSync FIFO family but, according to Cypress' Mr. Charubin, the result introduced a new architecture which forced OEMs to alter board layout and lengthened first word latency in speed sensitive applications to 13 clock cycles. Cypress said by adhering to the old FIFO standard, a strategy made possible by subsequent process technology adjustments, the DeepSync parts cut latency by nearly six times compared to its earlier parts.

IDT paints a different picture however. IDT FIFO marketing manager John Gudmundson said his company recognized a fundamental change facing the industry as demand for denser chips escalated: namely a shift from the dual-ported architecture favored by Cypress to what he termed a more elegant SRAM-based design.

According to Mr. Gudmundson, the cry for 1M and even 4M FIFOs required a shift from the 6-transistor dual-ported architecture advocated under the old standard to the 4-transistor SRAM approach, clearing valuable die space to meet increasing density demands.

"We looked at the market and saw there was a need for a much larger product," said Mr. Gudmundson, adding that IDT plans to release both SRAM- and fusion memory-based 1M FIFOs next year.