ViewLogic tool hits all design levels

Electronic News, Nov 11, 1996 by Gale Bradley

Viewlogic Systems rolled out version 7.3 of its Workview Office suite running on Windows NT and gave highlights of the software's value to the sizable installed base of field programmable gate array/complex programmable logic device (FPGA/CPLD) design seats using Workview Office.

"Major field programmable gate array vendors have upgraded their installed base with Workview Office," the company said. Viewlogic is the leading supplier of FPGA design tools with more than 75 percent of the installed base for FPGA/CPLD design seats, according to Dataquest.

Viewlogic said vendors migrating their customers to Viewlogic's Workview Office include Lucent Technologies, Actel and Xilinx. Reasons for that vary, the company noted.

Lucent Technologies encourages the use of language-based design tools for its customers and so emphasizes the language-based design methodologies supported by Workview Office. "We are shipping Workview Office with our Foundry 9.0 for FPGA design," said Fred Koons, Lucent's manager of FPGA strategic marketing.

"Viewlogic engineers have worked with us to develop specific synthesis optimizations for our ORCA FPGA families, and we are now reselling it to our customers as part of Workview Office. We have also developed and support libraries for the Motive static timing analysis tool in Workview Office. Our customers who want to validate their ORCA FPGA designs within the system environment demand these types of high-performance tools," Mr. Koons said.

Version 7.3 features an encapsulated language-based design methodology with an "Intelliflow" feature that aims to have designers at all levels of expertise adopting language-based design.

Proven and tested FPGA design flows have been implemented for Actel, Altera, Lucent, Xilinx and other FPGA families, the company notes.

"Up to now, designers have had as much difficulty learning and managing the tools necessary for implementing language-based designs as they had dealing with language-based design issues," said Dave Orecchio, PC group marketing director. "As designers change the design or choose different target silicon, the Intelliflow guides them through the design process. Intelliflow manages tool interaction for designers so they can focus purely on design issues."

Intelliflow in version 7.3 provides detailed tutorials covering pure language and hardware description languages (HDLs) mixed with schematic-based FPGA design. The ability to manage language mixed with schematic-based design allows designers to gradually adopt high-level design methodology at a comfortable pace without jeopardizing their project schedules, the company says.

"Most FPGA designers today use schematic-based design methods," says Gary Smith, the electronic design automation (EDA) analyst at Dataquest. "Since Viewlogic has the largest share of users in this market segment, the company is well positioned to move FPGA designers to a language-based design methodology."

Within the suite is a revamped synthesis offering, ViewSynthesis 7.3, that provides "Synopsys-style" VHDL language and package coverage. Device-specific optimization and mapping is provided along with datapath inferencing, resource sharing, and automatic state machine recognition and optimization. ViewSynthesis 7.3 also supports XBLOX/LogiBlox, Actgen, Scuba and LPM. A spreadsheet-style environment is provided for automatic I/O pad insertion.

"ViewSynthesis did a great job," notes Dave Grace, senior field application engineer for Xilinx. "The new ViewSynthesis user interface is easy to use and produces high-quality results in both area and speed for my target Xilinx FPGA."

The state charts capability comes in a StateCAD Workview Office edition developed with Visual Software Solutions of and will be available from Viewlogic with 7.3. It's used as an input medium for language-based design and sold in conjunction with ViewSynthesis.

"Viewlogic selected the StateCAD product after an exhaustive study of the technology available on the market," Mr. Orecchio said, and Visual "convinced us that we needed to develop a strategic relationship and OEM agreement with them." From state diagrams, it produces synthesizable VHDL, Verilog, ABEL and C for synthesis and simulation, "eliminating manual translation efforts and coding errors."

The HDL is optimized through state assignment modes, look-ahead decoding, and multiple code styles. "Revision is a simple matter of fixing the graphical diagram and re-compiling to update the HDL," Viewlogic said.

As an overworked Intel engineer, responsible for validation of the Pentium processor, Rodrigo Escoto (the president of Visual Software Solutions) designed hardware that made extensive use of state machines and glue logic. StateCAD is now used worldwide by IBM, Intel, Motorola, AT&T, NASA, Xerox and others. StateCAD allows engineers at these companies to concentrate on design functionality and at the same time produce documentation painlessly, Mr. Escoto says.

Since FPGAs have to get on boards to be of use to anyone, Viewlogic ironically notes, Workview Office then brings in board/system design with XTKV, a signal integrity analysis tool, and Motive for static timing analysis, both tools with performance normally associated with Unix. Printed circuit board (PCB) interfaces are available for most PCB layout tools, including the most recent addition, the VeriBest PCB interface (EN, Design Software, Nov. 4).