EDA row — Synopsys withholds data

Electronic News, Nov 18, 1996 by Judy Erkanat

Mountain View, Calif.--Throwing a spanner into the works of electronic design automation (EDA) industry efforts to cooperate on establishing industry standards, Synopsys has just said no.

Sparking the controversy at last week's EDA Industry Council meeting, Synopsys president and CEO Aart de Geus addressed the 30-40 members present with his reasons for not delivering logic synthesis implementation rules. This was after Synopsys had handed over the synthesizable register transfer level (RTL) language subset, as promised, in September. According to Dr. de Geus, this fulfilled Synopsys' commitment to the project technical advisory board (PTAB).

The industry council is working on standardizing and identifying a common subset for interoperability. Synopsys had delivered Verilog and VHDL language subsets (EN, Sept. 30) to the industry council working group.

"The working group has the Synopsys contribution to determine what they want to do with the Synopsys de facto standard, go with it or expand on it," said a Synopsys spokesperson. "We delivered on schedule. The controversy is that, although Synopsys delivered the syntax, or exact language constructs, as promised, others want Synopsys to deliver how it actually implements the syntax. This is how we synthesize the information; the implementation rules. Synopsys feels the actual implementation of synthesis is our patented crown jewels, and our answer is no."

The dispute, said Synopsys, is over patent issues and Synopsys' stance that the implementation rules are proprietary software, giving the company its market presence.

"The line between description and implementation can be fuzzy," said Larry Woodson, senior VP of corporate marketing at Synopsys. "Six weeks ago, we got a patent for one of the ways synthesis is implemented. This defined the line between description and implementation. Some say Synopsys has patented the only way to implement synthesis, but Mentor got up and presented its alternative at the last council meeting, proving there are other ways."

Mr. Woodson felt the controversy was due to Synopsys' competitors wanting to freely license Synopsys' implementation rules into the market.

"Victor Berman, chair of the PTAB subcommittee, said in the meeting that the purpose of the standard was to describe building blocks for reuse and clearly define description, but not implementation," said Mr. Woodson.

Mr. Berman, coordinating chair of the synthesis interoperability working groups with the EDA Industry Council and systems architect at Cadence Design Systems, voiced his disappointment with the Synopsys stance.

"At last Tuesday's meeting, somewhat surprisingly, Synopsys decided to give a definitive answer on the enforcement of its patent, which has to do with a small part of the implementation semantic of logic synthesis," he said. "I was very disappointed, as I think most of the other people were, that Synopsys intended to enforce this. This really goes against the grain of the open standards process we have been trying to initiate. It is particularly unfortunate with respect to what has been going on with IP (intellectual property) distribution and the whole VSIA (Virtual Socket Interface Alliance) effort, a lot of which depends on the good faith of the participants to be reasonably open about their formats and the definition of how the tools interoperate together."

Mr. Berman disagreed with Synopsys' idea about its impact on the implementation aspect of the tools, which he felt is actually a very small part of the overall picture.

"Every implementation of logic synthesis in the industry has solved this problem one way or the other," said Mr. Berman. "So it is not really germane to that. The big issue here is whether people can work openly together or if some people are just going to lock the industry into an old standard. Because of its uncooperative position, I think the groups working on the logic synthesis standard are going to have look beyond Synopsys. In meetings Nov. 19 and 20, there will be discussions of going off in a different direction, so that we are not hampered by the closedness of the material from Synopsys. The important aspects are the industry really wants to look forward to a standard for the future that will meet the needs of the people who are building and distributing product."

Others at the meeting were equally discouraged by Synopsys' stand.

"The RTL synthesis language subset was part of the goal to enable design re-use," explained Dennis Brophy, standards program manager at Mentor Graphics. "Synopsys delivered subsets in syntax form, but if we really want to enable design reuse, the semantics expressed in the domain of synthesis are required. To take advantage of the billion-dollar fabs they are building, manufacturers need to address synthesis semantics currently missing from the language."

Mr. Brophy felt Synopsys was overreacting. "Most of the patent in question covers latch inference," he said. "I would not characterize the totality of what synthesis is in regards to implementation. But I still hope we can find a way to collaborate on this."