Three metal layers speed FPGA design and operation

Electronic News, Nov 18, 1996 by Andy Santoni

Santa Clara, Calif.--Using an all-metal, three-layer interconnect architecture, QuickLogic Corp. has developed a series of field-programmable gate arrays (FPGAs) that offer high speed and low price.

QuickLogic's ViaLink technology results in a programmable element that has low ON resistance and low capacitance, and therefore is fast. The metal-to-metal amorphous silicon antifuse technology also increases the number of programmable elements per usable logic gate compared with dielectric antifuse interconnect or static random-access memory (SRAM)-based FPGAs. This, in turn, solves routing and pinout maintenance problems, which increase cost and lengthen time-to-market.

By reducing the need to route many signal paths by hand to meet device timing requirements, ViaLink allows engineers to rely on high-level description languages (HDLs) to generate their designs. Greater flexibility in layout allows engineers to trust that a design generated by computer will not have "race conditions" that make a design unstable, and should help shift the design process from schematic capture to HDLs. "Our hardware is very friendly to HDLs," noted E. Thomas Hart, president and CEO of QuickLogic.

Higher gatecounts will persuade engineers to cross the Rubicon to HDL, said Mr. Hart. "Higher capacity programmable logic devices have driven design methodologies toward HDL synthesis and simulation," he said. When devices were smaller, schematic capture was fast enough. As devices get larger, design time stretches, and at some point engineers must cross over to HDLs to get designs done quickly. "We are excited about the advances in design productivity and time-to-market that our users will realize with HDLs."

In 1995, most new designs used from 4,000 to 6,000 gates, said Mr. Hart. This year, that has risen, as expected, to between 5,000 and 8,000 gates. The switch to HDL becomes necessary at 5,000 to 10,000 gates, said Mr. Hart, so he expects rapid acceptance of HDL over the next few years.

Last year, 80 percent of the market was in schematic mode, said Mr. Hart. This has dropped to 70 percent or even 60 percent this year, which denoted a rapid acceptance of HDL for FPGA design.

One reason HDL did not take hold sooner is that smaller programmable devices did not have enough routing resources. As a result, first-pass designs had to be checked by the engineer (or an outside design service) to insure that paths with critical timing restrictions got the resources they needed.

QuickLogic's pASIC FPGA families are well suited for HDL design because their architecture provides flexibility, speed and high utilization without requiring manual intervention of design tool output to achieve optimal design results, explained Mr. Hart. ViaLink increases routing resources enough that manual "tweaking" of a design is greatly reduced.

ViaLink technology provides an abundance of interconnect resources between the top two layers of a three-layer metal interconnect complementary metal-oxide semiconductor (CMOS) process. Moving the ViaLink antifuses over the silicon results in smaller die sizes, which reduces cost. The global connectivity of devices in QuickLogic's pASIC 2 family of FPGAs, combined with ViaLink's speed, results in a device family that can always route a design, maintain pinouts to a circuit board layout, and provide fast, stable timing. These features enable high speed and high device utilization for Verilog or VHDL designs, noted Edward Smith, QuickLogic's director of corporate marketing.

"We are the only company currently capable of offering a solution that can give synthesis the resources it needs to implement Verilog and VHDL designs efficiently," said Mr. Smith. "The manual manipulation required by the limited resources of competitors' reprogrammable devices is impractical with the level of abstraction of HDLs," he noted.

The variable grain size in a pASIC 2 logic cell allows a synthesis tool to maximize utilization on the die by using a cell for up to five independent functions, or for a single function with up to 14 inputs. The pASIC 2 family ranges from 3,000 to 20,000 usable gates, with datapath speeds exceeding 200 megahertz and counter speeds over 150MHz.

With ViaLink, antifuses are placed between metal layers (Figure 1), instead of taking space on device substrates, as with competing technologies. Placing routing tracks and programming elements in the second and third layers of metal results in a 50 percent reduction in die size over a two-layer metal technology, noted John Birkner, VP for CAE tools at QuickLogic. Figure 2 compares two-layer metal interconnect devices with resources adjacent to the logic cell and three-layer metal interconnect devices with resources placed above the logic cell. Figure 3 shows the complete pASIC 2 logic cell, which consists of two 6-input AND gates, four 2-input AND gates, six two-to-one multiplexers and one D flip-flop with asynchronous preset and clear controls.

Figure 4 shows a cross-section scanning electron microscope (SEM) photograph of the ViaLink antifuse establishing a connection between two metal routing tracks. When programmed, the ViaLink resistance changes from over 1 gigohm to less than 50 ohms. When unprogrammed, a ViaLink antifuse adds less than 1 femtofarad (fF) of capacitance across the two lines it can potentially connect. In pASIC 2 FPGAs, routing capacitance was reduced further through a change in the programming link accessing circuitry. The resulting RC time constant associated with routing wires inside the devices is as small as 8.5 x 10-12 second, allowing very-high-speed signal propagation and consistent timing after re-routing signal paths during design iteration.