QuickLogic teams with TSMC; sets hybrid PLD version

Electronic News, Nov 25, 1996 by Peter Brown

Santa Clara, Calif.--QuickLogic will today announce a foundry agreement with Taiwan Semiconductor Manufacturing Company (TSMC), QuickLogic's second foundry agreement is in its eight-year of existence. In addition, QuickLogic revealed plans to roll out its own version of a hybrid programmable logic device (PLD)--combining application specific integrated circuit (ASIC) functionality with a field programmable gate array (FPGA).

TSMC will work jointly with QuickLogic to integrate QuickLogic's antifuse technology onto TSMC's 0.5-micron, three-layer metal process, according to Ed Smith, director of corporate marketing for QuickLogic. The company will migrate from a 0.65-micron to a 0.5-micron process with the foundry agreement. QuickLogic said this shrink in geometry will enable the company to reduce the die size of its devices by 44 percent.

"This partnership not only ensures a plentiful supply of 8-inch (200 millimeter) wafers at 0.5-micron, but soon for TSMC's 0.35-micron process and beyond," said E. Thomas Hart, president and CEO. "QuickLogic's metal-layer ViaLink antifuse hosted on this 0.5-micron CMOS process will enable us to manufacture the very high density members of our pASIC 2 family with die sizes smaller than any comparable competing product. This means that designers will finally be able to cost effectively obtain FPGAs over 10,000 usable gates without having to sacrifice performance or usability."

The move from six-inch to eight-inch wafers will allow QuickLogic to reduce the price of its FPGAs as well, Mr. Smith said. The 9,000-usable gate pASIC 2 device will be the initial product manufactured in the TSMC fab with the other members to closely follow, QuickLogic said.

Meanwhile, QuickLogic revealed its plans to create a hybrid PLD device combining FPGA and ASIC functionality. QuickLogic would not give specifics to its plans. However, Mr. Smith confirmed the company would not be licensing Synopsys' cell-based architecture nor would QuickLogic be doing its ASIC work in-house.

Coupled with a hard-wired ASIC, the FPGA becomes 10 times as dense while operating faster than a normal FPGA. QuickLogic said it will introduce its product line in mid-1997.