Systems-on-a-chip creates new requirements

Electronic News, Jan 13, 1997 by Emil Girczyc

The advent of systems-on-a-chip challenges us to meet a new and rigorous set of requirements regarding the verification of these designs if we are to overcome verification bottlenecks brought on by soaring design size and complexity. Design implementations that traditionally employed individual ICs for various components (e.g., microcontrollers, DSPs) are transitioning to maximum integration of functionality on a single chip; systems-on-a-chip is fast becoming a reality.

1-Size Doesn't Fit All

As design implementation and silicon technology advance, the traditional use of a single event-driven simulator throughout the design cycle presents serious drawbacks. "One size" doesn't fit all verification tasks; event-based simulation alone simply cannot achieve the requisite speed and capacity to meet the demands of the day. Design size, complexity and advanced design features prevent exhaustive simulation--running enough vectors is a difficult process and a calculated risk. Traditional HDL-based simulation is painfully slow for high data volume applications; a single second of MPEG video can take several days of simulation. If real-time for the target application is 54 million cycles and the simulator runs at 150 cycles per second, the mismatch between the design technology and the verification technology can become a source of costly uncertainties.

Essentially, any single verification tool represents a trade-off between the parameters of speed, flexibility, coverage, interactivity and detail; the evolution of design verification methodologies illustrates that it isn't possible to maximize all these characteristics in a single tool. However, it is possible to compose an ensemble of verification tools, individually optimized for particular tasks within the verification cycle. In fact, it is a necessity in order to achieve high confidence in systems-on-a-chip designs that we address verification with an integrated tool methodology that matches the design methodology.

Technology Mix

The foundation for developing a new and effective verification methodology will include a mix of technologies: event-based simulation, cycle-based simulation, language-neutral simulation, high performance models and libraries, emulation and simulation acceleration, static-timing analysis, and formal verification. It is important to note that a predominantly synchronous design style and a synthesis-based coding discipline are essential to making use of many of these technologies.

The need for event-based simulation will persist as it continues to be the most appropriate tool within many methodologies for refining the design concept, regression testing of design blocks, and for gate-level sign-off simulation, without imposing restrictions on design style. Cycle-based simulation provides a tremendous performance increase over event-based, making it the ideal engine for extensive regression testing. The availability of models and libraries is critical to enabling core-based design and the integration of multiple IP blocks on a single chip. Demand for emulation rises along with the demand for real-time system verification, for designs requiring subjective analysis, and to verify products with a short product development cycle.

When comprehensive simulation is too costly or time-consuming, and exhaustive verification is required to ensure product integrity, users will feel the need for static methodologies. The combination of static-timing analysis and formal verification offers fast, exhaustive verification for both timing and functionality. Some users are already moving to static sign-off methods because they offer the performance required to meet time-to-market constraints and eliminate the need for test vectors. The increasing adoption of a synthesis-based design discipline reaps the benefits of both synthesis tools and those verification tools optimized for predominantly synchronous designs, allowing designers to separate timing verification from functional verification.

Seamless Tool Chain

Design teams will create individual methodologies that utilize a set of verification tools suited to their particular application and design style. But, critical to any methodology are a set of highly effective point tools and a smooth transition for designers and design data between those tools to create a seamless tool chain. The EDA vendor can add the highest value to this equation by providing robust tools, relieving users of the burden of tool integration by delivering a consistent and streamlined design verification environment, and facilitating the use of these tools in the designers' environment such that they can verify early and often.

In order to achieve essential productivity gains, designers have chosen to work at the higher, register-transfer level (RTL) and adapt their designs within the constraints required for synthesis, such that they can capitalize on the benefits that this methodology provides. Designs are becoming more predominantly synchronous, and the dominance of RTL design and logic synthesis, which separate creation of the functional description from the timing-dependent implementation, have enabled designers to separately verify function and timing. These developments pave the way for adoption of technologies such as cycle-based verification, static-timing analysis and formal verification. The adaptation of coding styles and verification tools to a synthesis-based discipline will accelerate the development of a successful systems-on-a-chip verification methodology.