Advances in technology bring DFT to designers

Electronic News, Jan 13, 1997 by Mark Milligan

Implementing design-for-testability (DFT) techniques is one of the critical problems design engineers will face as silicon geometries plunge into the deep-submicron realm. Some companies have routinely incorporated test into their design cycles, but for most designers, test takes a back seat to other, more pressing concerns.

But intricate silicon designs demand test, and if not implemented properly, test structures can adversely affect a device's performance. Though increasing complexity and shrinking time-to-market windows means DFT is here to stay, the question naturally arises--how can the EDA industry make implementing test as painless as possible? If DFT and automatic test pattern generation (ATPG) are to become part of a designer's concerns, several conditions must be met.

First of all, tools must have minimal impact on design. Though this requirement sounds obvious, strict DFT rules are sometimes difficult to implement without design changes. Early versions of DFT tools (including some tools still on the market) often imposed design restrictions that prevented many design engineers from seriously considering DFT. These limitations often demanded restrictive clocking schemes and excluded the use of asynchronous logic, embedded memories or internal three-state busses. This greatly limited the number of designs that could accommodate DFT. It is important, therefore, that test tools remain flexible enough to let design engineers implement test structures while meeting their functional requirements, maintaining chip performance and satisfying area constraints.

The Earlier the Better

A successful DFT tool must also uncover problems as early as possible in the design process. Fortunately, advances in DFT techniques fit nicely with this requirement. Because many IC designers already use high-level techniques and logic synthesis for at least a portion of their designs, performing testability analysis at the RTL level, well before logic synthesis, can be a natural transition. With previous generation tools, DFT problems were identified only at the gate level, after many months of RTL design, simulation and synthesis work.

Finding problems during the early coding of an RTL design helps in two ways. First, it improves the quality of the resulting design. Previously, when problems were discovered late in the process, designers often decided not to fix the DFT problems, because making a change could have a major impact on the project schedule. This often resulted in poor fault coverage. Second, finding test problems early in the process can reduce design iteration time. If high fault coverage is a requirement for a project, then it is important to reduce the cycle time between finding the problems and correcting them. The figure below illustrates the improvement that can be made by performing testability analysis at the RTL level by using a tool such as Viewlogic's Sunrise High-Level Testability Checker (HTX) tool.

Seamless Integration

Successful DFT implementation fits closely into the design flow. A close fit means that test data can be passed back into the design environment, including ASIC vendor design flows. To ensure a proper fit into an existing design environment, RTL analysis must take into account the coding style used by the logic synthesis tool. Standard, language based-formats such as Verilog must also be used to ensure successful design transfer between tools.

Finally, the DFT methodology must integrate with "golden" simulation environments such as Verilog, so that ATPG patterns won't interfere with sign-off requirements. Additional interfaces may be required as well, such as links to floor-planners and placement tools for optimized scan chain ordering, static timing analysis tools, such as Viewlogic's Motive, and test pattern interfaces to common tester data formats via languages, such as Summit Design Automation's WGL.

Easy Does It

Another critical requirement for DFT tools is that they be easy to use. Design engineers must perform analysis on their circuits during many phases of the design and have no time to wrestle with difficult DFT software. In the past, most DFT tools were strictly command-line and script-oriented. The early users were primarily dedicated DFT or test engineers, who could afford to become DFT experts. But as more design engineers adopt DFT techniques, ease of use is an essential requirement. The graphical test debugging environment is a prime example of how ease of use can be integrated into DFT tools.

In summary, EDA technology has made significant strides recently to make it easier for design engineers to adopt DFT. As device complexity and shrinking time-to-market prod more designers into the DFT camp, these advances will be welcome news to busy engineers who might be unfamiliar with the world of test.