Complexity, geometries challenge designers

Electronic News, Jan 13, 1997 by Vic Kulkarni

Today's IC designs are pushing the limits of deep-submicron (DSM) technology, defined as below 0.5-micron. Process technology is rapidly moving to 0.13-micron feature sizes for CMOS semiconductors, and these shrinking silicon geometries pose new design challenges. Gordon Moore's Law simply states that every 18 months, the number of gates per area of silicon will double. The Sematech roadmap states that by the year 2001, leading-edge ICs will have more than 64 million transistors.

Chip designers faced with these higher levels of complexity and shrinking geometries must also surmount increasing time-to-market pressures. As a result, there is a crucial need for a new standard of IC design productivity, a new generation of ICDA (integrated circuit design automation) tools and a new paradigm of design practices to meet these challenges.

There are several key design issues driving this ICDA paradigm shift. Designers of complex ICs such as microprocessors, mixed-signal devices or digital signal processors (DSPs), face conflicting tradeoffs between parameters such as timing, power and area. Secondly, the sequential processes performed in the design iteration loop (synthesis, logic simulation, floorplanning, place and route) yield results that often do not converge. And finally, "over the wall" design approaches in which the front-end synthesized design is-more-IC-handed-off to the physical design team, are no longer efficient. This process is too slow and cumbersome, and higher chip densities have made impractical the huge amount of data going back and forth.

Design Gets Physical

To streamline the design flow for today's DSM chips, a new paradigm for ICDA tools and processes must meet the following requirements: design planning tools must accurately estimate and optimize multiple chip constraints up front in the design flow; and synthesis, floorplanning and place and route must all work together. Shrinking silicon geometries have longer interconnects and managing interconnects in the physical design becomes the dominant factor in today's DSM designs.

The top-down design methodology of the 1980s worked well because gate-delay dominant designs (0.5-micron and above technology) had a clear separation between the front-end and the back-end design flow. The design was driven from the front-end database and by using this "golden" database, ASIC, and IC vendors fabricated working silicon.

However, with today's shift from gate-delay dominant to interconnect-dominant designs, spurred by shrinking silicon geometries, a new golden netlist has emerged; one that is driven, from the outset, by physical design constraints. If physical effects are not represented early in the design cycle, ICs can not meet today's stringent performance targets. Therefore, back-end physical analysis has now emerged as the center of the design universe.

Managing Interconnect

Timing and performance optimization has traditionally been performed by front-end design tools and this process has achieved good results for gate-delay dominant designs. However, with deep-submicron designs, interconnect effects play an increasingly important role in circuit performance because at silicon process rules below 0.5-micron, effects such as distributed capacitance and resistance for long metal lines, more signal cross-coupling between parallel conductors, switching power, electromigration effects and unwanted electromagnetic interference that influences signal integrity start dominating in overall chip performance.

Extraction of interconnect information is another key issue for DSM designs, since interconnect delays represent the majority of delays within a design. To meet IC performance targets, interconnect effects must be accurately modeled and then fed into simulation. Since a single-line interconnect represents distributed resistance and capacitance (RC) values, it is critical that accurate RC values are extracted from the physical layout with a tool such as Avant!'s Star, and accurate simulation results can then be obtained using a circuit simulator such as Star-HSpice or Star-ADM.

Sematech, has demonstrated support for a new IC design paradigm and has challenged the EDA industry to create forward-looking, timing-driven design tools for 0.25-micron and below feature sizes. The goal is to eliminate the time-consuming iterative design process, and offer tools which can predict the impact of the next phase of a design. Avant! is uniquely positioned to be the leader in providing the ICDA tool suite for this new design paradigm.