ARC unveils Altera 20K-based development system

Electronic News, Feb 3, 1997 by Jim DeTar

San Jose, Calif.--High-end programmable logic comes together with RISC microprocessor technology in Argonaut RISC Cores (ARC) application specific ICs (ASICs). ARC unveiled the Hardware Development System powered by Altera's FLEX 10,000 FPGA at the recent Design Supercon conference here and said a previously announced partnership with Rockwell's Brooktree division for a new 3-D processor is about to yield silicon.

The ARC microprocessor core is touted by Argonaut as the industry's "first customizable processor," allowing the engineer to modify the instruction set to a particular application. In order to evaluate this capability, Argonaut created a hardware development system that utilizes Altera's FLEX 10K FPGA (field programmable gate array). A single FLEX 10K houses the ARC microprocessor core, extensions, memory cache, arbitrator and sequencer for external memory, and a PC interface.

The engineer can make modifications to the ARC core, and in real time implement those changes directly in the FLEX device. This allows designers to evaluate design trade-offs in performance and silicon area, and begin writing software prior to committing to custom silicon.

Argonaut president and CEO Robert L. Terwilliger outlined the strategy behind the ARC core in an interview.

"The people that have been most excited about the opportunity of ARC are companies where the silicon budget for ASIC is in the $10- to $50 million range over the life of the part," Mr. Terwilliger said. "Because of the additional efficiencies of an application specific processor like ARC, we can reduce that budget by 20 percent. If they have a $10 million silicon budget using general purpose microprocessors in embedded systems, by replacing it with ARC, they reduce that to $8-or $9 million very quickly, some higher depending on the size of the chip."

Mr. Terwilliger said that a previously announced partnership with Brooktree to develop a 3-D chip is progressing. "The first customers are implementing the core. They have completed the design and are expecting silicon in a few weeks."

Mr Terwilliger also revealed the company is on the verge of announcing two new licensees for its ARC core. "The first wants to do a press announcement the first week of February and the other the first week of March. We hope to announce three to four new licensees," in the near future, Mr. Terwilliger said. "There is one brand name--one of the top 10, maybe one of the top five--ASIC vendors, and a second company in the graphics area--Microtree, a smaller company that will introduce products in the graphics area as well.

"In order to be application specific--at least our view of application specific--the company needs to have both hardware and software environments in order to implement and make changes quickly. As we looked at options software simulation was too slow. Other options are something like a Quickturn box or rapid prototyping like Chip Express does, or spending $80,000 to do silicon prototyping.

"What we've been able to bring to market is a situation where an engineer can synthesize and implement those using Altera 10000 technology and have proof of concept in 8 hours. If you look at cost factors, silicon prototyping is $80,000. Chip Express costs $40,000," Mr. Terwilliger asserted. "This system sells for $5,000. It accomplishes what we wanted to achieve."

Richard Derrill, Altera marketing program manager, commented "Because ARC represents a whole host of cores, the user can modify the core by adding functional blocks because it is available in synthesizable code."