SLDRAM - a scalable high-performance dynamic RAM interface

Electronic News, Feb 3, 1997 by Farhad Tabrizi, David B. Gustavson

Faster processors and higher performance graphics are pushing hard against memory speed and bandwidth. At the same time, DRAM density is increasing faster than DRAM capacity requirements, which should mean fewer but larger DRAM chips in typical products.

These requirements can only be satisfied by greatly increasing the DRAM chip, package, and controller bandwidth. Though ultimately the connection to memory may need to use point-to-point connections instead of buses, it's possible to do a few more product generations based on memory buses, if those buses are carefully designed.

SLDRAM adapted the IEEE Standard 1596.4 RamLink architecture, which is based on point-to-point connections, and a rather general communication model that also supports I/O and bridges, to optimize it for use in the carefully controlled environment appropriate for modern DRAM arrays. (MicroUnity's MediaChannel was another simplification of RamLink, which preserved the point-to-point connection architecture for gigabyte-per-second speeds, but was optimized for processor/controller rather than for direct implementation in DRAM chips.)

This adapted architecture is being standardized in the IEEE as Project P1596.7, which has a document about to go out for sponsor ballot, the last stage before final submission to the IEEE standards board.

Meanwhile, the SLDRAM Consortium has turned its attention to detailed physical design and optimization for use in production DRAM parts. Nearly all the world's DRAM manufacturers have joined in this effort, which is also being helped by testing companies, computer manufacturers, connector OEMs and others who expect to play significant roles in the production and use of DRAM in coming generations.

The scalability strategy of SLDRAM is based on two buses: a narrow uni-directional command/address bus, and a wider bi-directional data bus. The system can scale up in a modular way by replicating these buses in pairs, which leads to a single expansion module type for all system sizes. Alternately, it can scale more efficiently by replicating the data buses only, using the command/address bus to drive multiple DRAMs that may be on several data buses.

An elegant addressing and initialization scheme eliminates the need for fast chip-select wiring, and the protocols are entirely packet based, with none of the traditional RAS/CAS strobes used in previous generations.

First chips are expected in Q497, with production phasing in gradually in 1998. Parallel efforts for test chip development are in progress, and the schedule for test chip samples is Q397.

SLDRAM Advantages

As a high performance DRAM solution, SLDRAM offers many advantages. First, the open standard solution enables industry adoption without requiring the prohibitive licensing fees of proprietary solutions. This approach of providing a standardized solution without requiring expensive licensing fees has historically proven to be an effective strategy for obtaining broad market acceptance.

The Intel PCI standard is just one example of this successful approach. Further, by eliminating high licensing fees, the cost of an SLDRAM is immediately reduced relative to any proprietary solution. This lower overhead will make it economically feasible to convert production to SLDRAMs at an earlier date, facilitating earlier market and manufacturing transitions than a proprietary solution.

A second advantage of SLDRAM is the tremendous supplier support. With sixteen DRAM supplier members, SLDRAM has greater support than any other high speed DRAM alternative. Historically, product availability and second sourcing have been the key to establishing commodity solutions.

Further, since many suppliers and OEMs have been involved in the development of the SLDRAM standard, the research and development does not rely on the expertise and resources of a single company. This involvement will pay off as the hardware development phase begins, since design and implementation will not be bottlenecked by spreading the resources of an individual company across the entire DRAM industry.

The combined technical, financial, and manufacturing resources of the suppliers will also guarantee device samples and limited production at the earliest possible date.

The architecture and protocol of the SLDRAM create many advantages. The split command and data bus, the multi-bank architecture approach, the separate internal read/write data paths, the efficient protocol, the fast waveform settling, the dual echo clocks and the clock synchronization scheme all combine to minimize unused clock cycles on the data bus. These features enable the bus efficiency to approach 100 percent.

The SLDRAM architecture capitalizes on the combined experience of many DRAM architects to provide an optimum solution with regard to die size and power dissipation. As a result, the entry level SLDRAMs will immediately be cost competitive with 64-megabit SDRAMs, and the core power dissipation is only 0.6W. This low power dissipation keeps device junction temperatures low, which improves device reliability and the yield for meeting refresh specs.