Rambus technology use in high bandwidth DRAMs

Electronic News, Feb 3, 1997 by Richard Crisp

The information processing industry has recently changed its focus to media-oriented processing. Supporting multimedia applications has greatly increased the processing bandwidth requirements of the next generation of processors and system controllers.

Speeding up processor cores without increasing memory bandwidth results in unrealized performance. Unfortunately, increasing cache size alone is insufficient to sustain the memory bandwidth demands, as higher main memory bandwidth is also required. Rambus DRAMs are the highest bandwidth DRAMs and are currently in volume production in products such as the Nintendo 64 game machine, named "Machine of the Year" by Time magazine in 1996.

Rambus DRAMs

Rambus DRAMs (RDRAMs) have numerous advantages over conventional devices. They offer the highest pin bandwidth in production (currently at 600 megabits-per-second-per-pin scaling to 800Ms/pin in 1998), the highest fill rate, and the lowest pin count of all the high bandwidth DRAM options.

RDRAM devices and compatible logic devices connect to the Rambus Channel which is a simple but reliable bus. The bus and its associated elements (also known as the physical layer), feature separate transmit and receive clocks, Rambus Signaling Logic (RSL) and simple, low pin-count modules. Using a bus rather than a matrix topology permits configuration dependent loading variations to be avoided. This allows each pin of the Rambus Channel to operate at 600Ms and higher rather being limited to the 40 to 100Ms of conventional DRAMs in system applications.

The higher pin bandwidth results from exploiting the Rambus Interface's properties of equal fan-out, load and propagation velocity in combination with award-winning advanced circuit design concepts. The high pin bandwidth permits very low pin-count controllers to be developed, enabling significant cost savings in the components, printed circuit board (PCB) area and module/socket subsystems.

The lower component manufacturing cost results for two reasons: die size and test time. Minimizing the number of I/O pins necessarily reduces the silicon area required to build a complete DRAM or controller die. The high bandwidth into the DRAM core also permits device testing to be performed faster, further reducing manufacturing cost. The I/O pin reduction saves PCB area and minimizes the size and cost of sockets as well.

The low pin-count and high bandwidth enable simpler PCB design, permitting the Nintendo 64 to operate at 500Ms/pin on a two-layer PCB. By using 16M RDRAM technology, rather than 8M synchronous graphics RAM (SGRAM), Nintendo reduced system cost and fit it into a smaller box.

Since it takes twice as many SGRAMs per megabyte as 16M RDRAM devices, the packaging, burn-in and testing costs of SGRAM are duplicated, creating an inherently costlier component manufacturing infrastructure. Furthermore the area/bit of SGRAMs is larger than RDRAM devices, because supporting the 32-bit organization and the 100-pin external interface requires significant additional die area. Finally, the pad limited system control chip of the Nintendo 64 had a much smaller die because 80 pins were saved by using RDRAM devices instead of SGRAMs.

Next generation 128-bit 3-D graphics controllers using SGRAM or EDO require in excess of 200 pins for a gigabyte-per-second memory interface. But Rambus based controllers need only 62 pins for the same or higher performance, greatly reducing the cost of the controller and minimizing PC board area.

Industry Transformation

About 20 years ago, the DRAM market was in its early stages of evolution. The dominant applications were proprietary, large computers, such as mainframes, and minicomputers. At that time, DRAM bandwidth and density were low. The primary problem facing the system designer was building a memory system of sufficient capacity economically using components available from multiple sources. The JEDEC memory subcommittee was formed around that time to standardize the pinouts of DRAMs, providing a valuable service to the industry.

In the past three to four years, the fabrication technology which has enabled 16 and 64M DRAMs has also brought 200MHz-plus processors to the market. The typical memory system today may have two to 16 DRAMs delivering hundreds to thousands of MB-per-second to satisfy the demands of the application. To avoid needing hundreds of pins for the memory interface on the next generation of controllers, the pin bandwidth must be scaled to near the gigabaud rate.

Just a few years ago, it was adequate to only standardize I/O levels, pinouts and mechanical outlines of DRAMs and modules, but today an entire interface solution must be standardized to allow high volume systems to operate at gigabaud rates. Further compounding the problem is that the typical life cycle of a generation of system components has shrunk from three years to a year or less today. For standards committees this poses a vexing problem.

The development activities now necessary to define high bandwidth memory components and subsystems go way beyond what is supportable by a committee. They simply have too little staffing and move too slowly. The solution to today's system memory problems requires the full-time effort of a dedicated, centrally managed team in the same way that the design of a modern microprocessor does.