Memory technology still needs to 'catch up.'

Electronic News, Feb 3, 1997 by Andre Hassan

Today's CPUs, graphics and communications controllers are running at core speeds in excess of 200MHz, will reach 500MHz shortly and could approach 1GHz core operation speed by the end of the decade. Unfortunately, memory technology has not kept up.

Though several attempts have been made at seizing the opportunity, most DRAM manufacturers have opted to extend the life of the same old DRAM core. Some offered conventional DRAM extensions, such as wide, fast, and extended data out (EDO) versions, all of which are incremental modifications to existing DRAMs.

Others offered evolutionary alternatives, such as clocked synchronous operation (synchronous DRAM and synchronous graphics RAM). Here, they've added a contemporary interface onto the classic RAM architecture. Windows RAM (WRAM), for example, is simply a recasting of video RAM (VRAM), which is itself based on traditional DRAM. And Rambus DRAM (RDRAM), a revolutionary alternative, defines a new interface concept mated to standard DRAM. All of these alternatives modify the interface of the DRAM while retaining its fundamentally slow core.

Many of today's applications are characterized by several independent processes sharing a common memory. In such cases, controllers will time multiplex each process' access, giving each a turn to read or write in fast, short, memory bursts. The problem is, each process is typically looking for data in different "rows," and conventional DRAMs and their new DRAM derivatives cannot accommodate the processes without repeated, lengthy, row-access latencies.

Thus, the proportion of time that the memory is actually reading or writing shrinks with the increased frequency of row-access operations. As more processes are added, net, or useful, bandwidth decreases further.

Under these circumstances, DRAM innovations that deliver relatively high peak bandwidth are burdened by a high percentage of full, row-access delays. Memory performance consists of two components: high peak bandwidth and low latency. The solution to high peak bandwidth is obvious--increasing the data strobe rate takes care of that. Low latency is a more critical problem, and a common solution is longer transfers.

If the burst transfer size is increased for each read or write operation, then net bandwidth will also increase because useful operations occur longer while latencies remain the same. There is, however, a limit to how large the transfer size can be made, because the larger transfer size reduces the multiplex switching rate and causes the queued processes to wait longer for their chance at memory access. As a result, designers make a difficult trade-off between bandwidth, buffer size and transfer lengths.

A DRAM architecture that can reduce both the frequency and duration of row-access operations will allow greater net bandwidth at smaller transfer sizes. As a result, designers need to worry less about trading off bandwidth against buffer size and transfer length. They can choose smaller buffers and transfer lengths and still achieve high net bandwidth.

MoSys solves both bandwidth and latency problems with a Multibank architecture, which is a multiple bank DRAM core design with excess of 1-gigabyte-per-second internal data bandwidth and multiple internal DRAM banks, where any number of banks can be active, at the same time, on the same device.

Each active bank can have a different row address selected. As processes are multiplexed, successive accesses are frequently to different banks, but typically the required rows in those banks are already active so the latencies involved are much shorter. And, if an access is to a row address that is not active, the row-access operation can occur in parallel with a read or write operation. Thus, part of its latency duration is hidden during another useful operation.

A multi-process memory bank hit model, where several processes are generating independent random address accesses, can be described as follows: PHIT

100 x (1-1/B)N-1

Where PHIT is column access hit percentage, B is the number of banks and N is the number of processes.

A two-bank memory device with two processes will have a bank hit rate of 100 x (1- 1/2)2-1

50 percent. Increasing the number of processes to four reduces the hit rate to 12.5 percent. A multiple bank design, even with only eight banks, would maintain a hit rate of 87.5 percent and 67 percent for two and four processes, respectively. In addition to solving the bandwidth and latency problems, this architecture has the additional advantages of fine granularity and built-in redundancy making it suitable for cost efficient manufacturing.

MoSys believes that high-capacity DRAM memory must adapt architecturally to system needs rather than vice versa. As such, MoSys developed the Multibank DRAM core architecture which is organized the way systems use memory; leads rather than lags system bandwidth demand; and conforms to industry standard interfaces.

The MoSys Multibank core architecture is applicable to any DRAM core or any I/O interface. MoSys has already applied this technology in its MDRAM and MCache products and soon will introduce SGRAM and RDRAM devices based on this revolutionary core.