Double Data Rate technology vying for prominence

Electronic News, Feb 3, 1997 by Brett Etter

Unless high-speed microprocessors are kept from starving for data, system throughput will fall far short of its maximum potential.

In future generations of single processor systems, traditional memory chips may not be fast enough to do this. A promising solution is memory devices that use Double Data Rate (DDR) technology, a circuit technique already in use and destined to grow to prominence.

System performance issues are clearly and urgently driving the need for DDR technology in DRAMs. In PCs with a single CPU (about 70 percent of the total market), system performance is affected by two primary factors: internal microprocessor speed and bus speed, which are related by a clock multiplication factor.

For example, the Intel Pentium 133MHz processor uses a 2x multiplier because it has a 66MHz data bus, but runs at 133MHz internally. Other currently available Pentium processors have internal clock/bus speed multipliers that range from 1.5x (90MHz version) to 3x (200MHz Pentium).

The best balance between processor speed and bus speed for optimized system performance is realized at the 3x point. Above the 3x multiplier, the processor becomes so starved for data that significant system performance improvements can't be achieved.

Thus, as processor speeds continue to rise beyond 200MHz, the memory bus speed, and, subsequently, bandwidth, must increase to maintain the internal clock/bus speed ratio at or below 3x.

Synchronous operation

Synchronous memory devices achieve their performance via various circuit techniques, but the one thing they have in common is that they all synchronize their operations to the rising edge of the clock. DDR carries this concept one step further, effectively doubling the maximum transfer speed and peak bandwidth of traditional devices by outputting data at twice the clock speed and transferring data on both the rising and falling edges of the clock.

Obviously, this causes the data valid time period of the device to be at least 50 percent shorter. The memory controller must have the capability to deal with the higher data throughput as well as the shorter valid data windows.

Prefetch architectures

Synchronous burst/pipelined memory devices, including all chips that use DDR technology, use architectures with prefetch circuits. These prefetch architecture devices are classified as xN parts, where x is the number of internal data lines from the memory array to the output stages divided by the number of external data lines.

For example, a traditional 2-megabit x 8-bit DRAM has eight external data lines corresponding to eight internal data lines and provides only one byte of data per address. Using the xN rule, a 2N prefetch version of this DRAM device would have 16 internal data lines and a 16-bit (first in/first out) FIFO register that could provide bursts of up to two bytes of data per address. Likewise, an 8N variant would have 64 internal data lines and a 64-bit FIFO register that could provide bursts of up to eight bytes of data per address.

One aspect of the xN architecture is that the prefetch queue is filled for each address. When the memory controller does not need every piece of data that was retrieved, extra clock cycles must be allocated to flushing the unused data from the FIFO register, during which time no further data transfers are possible. In a 4N device, for instance, if the memory controller only needs one piece of data, then three additional clocks are required to flush the register of pieces of data that are not needed.

Another aspect of the xN architecture that has been a concern is increased die size and chip complexity. The higher that x is, the greater the number of data lines the chip must have for accessing the memory array, and the more internal registers it must have.

On lower density memory devices, such as 4M parts, the complications of prefetch implementations can significantly expand die size. However, at the 64M level, the die size penalty is only a small percentage, so IC makers now find it more feasible to implement this architecture. While very few memory devices use a prefetch architecture today, the capability of increasing the bus frequency, due to DDR technology, will drive implementation of the prefetch architecture into more memories.

Applying DDR technology

Will system designers be able to use memory devices with these new circuit techniques to their maximum bandwidth potential? That depends on the architecture and operating characteristics of the CPU. That is, if the microprocessor and core logic chipset combination is designed with DDR devices in mind, then the processors can be manufactured to operate at significantly higher frequencies and still not be starved for data by exceeding the 3X multiplier.

As a result, system performance can continue to increase as operating frequencies rise. In fact, this technology is already in use in devices such as those based on the Rambus architecture. These devices are beginning to have an impact on the PC market, where low costs are of primary importance.