NOR-based flash leads promising memory designs

Electronic News, Feb 3, 1997 by Mike Seibert

Applications for flash memory vary greatly and will continue to evolve as flash memory technology evolves. Firmware applications still consume the majority of flash memory. Often referred to as the EPROM-replacement market, these are the applications that NOR flash dominates.

However, applications for very high density and large data/file storage have given an opportunity to the flash manufacturers to try alternative approaches to memory architectures and write/erase methods.

The predominant flash technology today, by volume, is still NOR-based with channel hot-electron injection write and Fowler-Nordheim (FN) tunnel erase. This approach to building flash memory is the most understood and can be used in the broadest range of applications, from firmware storage to mass storage.

New architectures are attempting to address specific weaknesses in the NOR approach, which while the most versatile flash architecture is not necessarily the most optimum for all applications, NOR technology offers high speed reads and byte write, but it also uses enough current for write operations to limit what can be written or erased in parallel. When handling large blocks of information, this can slow the write and erase times and reduce system performance.

Another improvement over NOR that these architectures are attempting to address is a smaller overall array area. By reducing the number of array contacts to the memory cells, the array can be made smaller.

NOR, NAND, AND and DINOR are all acronyms that refer to the wired logic used when wiring th memory arrays. The Boolean function is defined by the logic needed to access the flash cell on the digit line (or column) of the array.

NOR implements an "OR" function on the digit line, meaning that cell A, or cell B or cell C needs to be "on" to access the desired data. This is the type of memory array structure that most engineers are familiar with, and it is used on most memory devices such as DRAM, SRAM, EPROM, EEPROM and Flash (see figure one).

The NAND Flash uses an "AND" function along the digit lines together with two select lines to enable the local digit line to have access to the main digit line. In this case, cell A, cell B and cell C must be "on" to access cell D. The AND cells are turned on with polysilicon select gates which don't require metal contacts. The contact to the digit line is needed only for a group of select lines and their corresponding flash cells (see figure two).

AND and DINOR are really hybrids of true NOR and NAND architectures. They take different approaches to the task of reducing array contacts, with AND using two select lines and DINOR using one (see figures three and four).

The second differentiating attribute of non-NOR architecture is its method of writing the floating storage cell that makes up the memory element of flash memory. There are many variations in the details of the writing method, but it boils down to either channel hot electron injection (CHEI) or Fowler-Nordheim (FN) tunneling.

Channel hot electron injection

Channel hot electron injection is the mainstream of flash technology today. It uses a write method very similar to EPROM. CHEI is a higher-current write operation than FN tunneling, but it gives much better threshold control and byte write speeds. Since it is high current, a large number of bytes can't be programmed in parallel, because of excess current demands that it would place on battery systems.

NOR has proven to be the best technology for code and small data storage applications. Byte writes can be done at random at relatively good write speeds, typically around 10 microseconds or better. Write/erase endurance is typically in the 10,000 to 100,000 cycle range which is more than adequate for these types of applications.

Channel FN tunnel writes

Channel Fowler-Nordheim tunneling is used by NAND, AND and DINOR architectures. The FN tunnel approach has the advantage of being low current and potentially higher endurance, but the disadvantage of needing higher voltages in the memory array than CHEI. Tunneling from the floating gate transistor gate channel has been shown to be a difficult thing to control. The benefit of FN tunnel write is that since it is low current, writes can be done in parallel. So when storing large files, the effective write speed per byte can be quite fast.

One difficulty of the channel FN tunnel approach is that it is hard to accurately control the threshold levels used to sense a 1 or a 0 in the flash cell when using FN tunnel write. This can slow the read sense times and result in a slower device access time, although it is a lower cost technique than EEPROM, which uses two transistor gates and two tunnel oxide thickness.

Erases

All of these devices use FN tunnel erase from the floating gate storage elements to the substrate. This differs from EEPROM--which also uses FN tunnel erase--because EEPROM defines a special region in the floating gate channel for the tunneling to occur. Flash, on the other hand, uses the source or drain junction side of the floating gate as the tunneling region. This reduces cell area and cost significantly, but could also affect the endurance and retention capabilities of flash relative to EEPROM.