Serial Presence Detection poised for limelight

Electronic News, Feb 3, 1997 by Thomas P. Koenig, Nathan John

Presence detection is a mechanism designed for use by a host system to relate attributes of memory modules such as size, speed and technology. Historically, this has been made available via a Parallel Presence Detection (PPD) scheme, a process whereby dedicated pins are hardwired on the module in a manner which may be decoded by the host.

However, this process is limited in its ability to comprehend new memory technologies adopted onto the same physical module outline. This disadvantage can be overcome by implementing a technique known as Serial Presence Detection (SPD).

New memory module form factors are defined with a non-volatile storage device on them to contain the presence detection information. This method has the further advantage of providing a wealth of additional information about the module. Serial EEPROMs, for example, are well suited for implementing SPD because they can provide the non-volatile storage and the bus interface controller in one chip.

In the past, presence detection by a parallel means was accomplished by dedicating pins to depict the pertinent attributes of size, speed and technology. The typical 72-pin single in-line memory module (SIMM) uses five pins--two to relate speed, two dedicated to density and one to support recognition of error checking schemes.

The five-pin restriction severely limits the number of possible configurations and hinders the future expandability of the module definition. An example of this inflexibility exists on the 72-pin SIMM, which was defined prior to the advent of EDO DRAM. This problem manifests itself in older PCs which may exhibit erratic operation, or halt completely, if EDO SIMMs are installed.

SPD was developed to rectify these shortcomings. In order to implement SPD, a non-volatile memory is used on each memory module to hold the presence detection data. The non-volatile memory allows for hundreds or thousands of bits of data as opposed to the original five when using the typical 72-pin SIMM. SPD has been adopted onto various JEDEC-standard module form factors such as the 168-pin unbuffered dual in-line memory module (DIMM) and the 144-pin small outline DIMM (SODIMM).

One of the first attributes presented in SPD is the identifier for the module's fundamental memory technology, be it DRAM, synchronous DRAM, or another memory type. By incorporating SPD onto a module when it is first defined, new memory technologies can be adopted onto the same module form factor without risk of those problems now faced by SIMMs using EDO.

This is because the host system, knowing that the modules will have SPD, can now look for the particular identifier of the memory technology it is prepared to accommodate. The system can flash an error or warning message if an unrecognized technology identifier is seen. Furthermore, the SPD standard has provisions to allow for superset technologies such as those functionally backward-compatible with any given base technology. This facilitates evolutionary enhancements to existing technologies.

Since there are so many bits available for SPD data, a standardized method of organization was necessary. This was accomplished by arranging the SPD data in a series of table entries. Each table entry, typically one or two bytes, represents one particular characteristic pertinent to the memory module--e.g. DRAM will have specific tables for module speed, architecture, addressing, refresh rates, etc.

Each table entry corresponds to a position on a look-up table specified in the JEDEC SPD standard. The number of bytes used to express a particular aspect of the module is fixed and defined by JEDEC. This address map for SPD is fixed so that the host system knows how to interpret the data and appropriately configure the memory controller. Industry standards have been developed, or are in process, for FPD, EDO, and synchronous memories.

An important step in the process of implementing SPD is to decide on the serial bus protocol to send and receive information to and from the module. There are several factors that are important in the choice of the best bus protocol for this application, including the number of pins required on the module, the effect on overall system architecture and the availability of off-the-shelf silicon. I2C is a bus protocol that addresses these requirements well and was chosen for the 144-pin SODIMM and 168-pin unbuffered DIMM.

When considering the new 168-pin unbuffered DIMM, the software addressing scheme in I2C allows up to eight modules to be installed into a system with only five interface pins: serial clock (SCL), serial data (SDA), and three SPD address pins (A0, A1, A2).

Figure 1 gives a typical application block diagram. It is also important to note that the SPD address pins on each module connector are tied statically and do not require I/O lines coming out of the processor or memory controller. This allows the host system to distinguish one memory expansion socket from another. Each socket can then be queried to determine if a module is present, and the SPD information can be accessed to identify the module's features.