New firm—Verysys—sets formal verification debuts

Electronic News, April 21, 1997

Formal verification is emerging as a hot technology area this year. Bell Labs Design Automation just brought out a new offering in the field (EN, April 7). In addition to Chrysalis Symbolic Design and Abstract Hardware, two start-ups in the field, EDA industry observers are looking for Mentor Graphics and Synopsys to enter the market.

Verysys was founded in Germany last year and opened an American office here last November. It has attracted $2 million in funding from individual investors in the U.S. and Europe, along with the Deutsche Bank and an agency of the German government.

The company is developing its initial products using technology obtained from Siemens of Germany. The VerysysProver line of formal verification products, including StructureProver, DesignProver and PropertyProver, will be unveiled at DAC in Anaheim, Calif.

Verysys is led by president and CEO Hans-Detlef Boesch, who most recently served as VP of marketing and engineering at Thesys Microelectronics and earlier worked at Intel, Hitachi, ES2 and LSI Logic. The VP of engineering is Ramayya Kumar, a former Siemens researcher. Jeffrey L. Langner, VP of U.S. sales, has held sales positions at LogicVision, Viewlogic Systems and Met-Software. Ulrich Koehler, VP of European sales, has held sales posts at Alcatel-Mietec, LSI Logic and Cirrus Logic.

The company employs 11 people in the U.S. and Germany, with plans to staff up to 25 by the end of the year. R&D will be carried out in Berlin, while management, marketing and sales will be run out of the U.S. office. "The music is playing here," Mr. Boesch said in an interview last week.

Verysys intends to market it calls "FeedForward" electronic design tools. The term is meant to connote proactive, forward-looking design tools, complementary to the existing design flow, which is largely based on a "feedback" approach.

Verysys is working with formal verification technology which has been in use for years within Siemens. "I am glad to welcome Verysys EDA as a technology associate," said Wolfram Buettner, senior director of the Siemens Corporate Technology department. "We are pleased about the worldwide market opportunities for our formal verification design tools that will be enlarged by the efforts of the Verysys team."

Verysys' StructureProver tool is said to be a high-speed package that certifies formally the structural equivalence of circuits at different levels of abstraction, arising from operations such as synthesis, optimizations, redesign, engineering change orders, last-minute changes, buffer insertions, library migration, test structure and clock-tree insertions.

Verysys plans to market its products first to potential customers in the U.S. and Europe, then to the Asian markets. The company plans on obtaining additional funding in 1998 and 1999, followed by an initial public offering in 2001. About the possibility of facing competition from the likes of Mentor Graphics and Synopsys, Mr. Boesch was sanguine. "I think it will be a challenge, but we are very dedicated to this market," he said.