Manufacturing Industry

Synopsys rolls 2 design tool entries

Electronic News, April 21, 1997

Sanjiv Kaul, VP of marketing for Synopsys' Design Tools group, said the company has been working on these products for some 18 months. A separate project with IBM technologists, initiated last year, is expected to yield commercial products in the second half of this year.

Synopsys 97 is intended to address the design of ICs with 0.18-micron geometries and 500MHz operating speeds, according to Mr. Kaul.

Synopsys said the new update includes more than 100 performance enhancements to over 20 Synopsys products. The Synopsys 97 release of Design Compiler features timing improvements for high-performance design and new area optimization techniques for cost-sensitive applications, the company said.

For 85 percent of the timing-critical designs tested, timing slack improved by 23 percent on average. The improved timing results, obtained with a one-pass compile step, would likely have required two or more passes previously. For 85 percent of the area-constrained designs, area is improved by an average of 18 percent.

Synopsys said one early user of Synopsys 97 has already taped out a chip. Mr. Kaul declined to identify the user, other than to say it is a "major microprocessor company." Synopsys said the company's design team was able to achieve a 10 percent performance improvement, meeting their timing goals, using Synopsys 97.

Synopsys 97 is now shipping, with pricing dependent on configuration and maintenance contract. For more information, visit the Synopsys Web site at http://www.synopsys.com/synopsys--97.>Synopsys' ECO Compiler is intended to work with Design Compiler. It is available immediately as an optional tool for Design Compiler users, at a list price of $100,000.

ECO Compiler is primarily intended for design teams that need to implement changes to a design following synthesis and place-and-route. The tool can also be used to implement changes to a synthesized netlist before layout, preserving the investment in optimization of critical paths. ECO Compiler can be used to make metal-layer-only changes to post-tape-out designs, enabling designers to change the design in the manufacturing stage and avoid costly respins.

"ECO Compiler took less than a day to implement a change which could have taken us a week to do by hand," said Minoru Takeno, manager at Fujitsu Telecommunications. "When you are only a few days before tape-out, such a tool is invaluable."