Intel aims to eliminate EEPROMs

Electronic News, April 21, 1997 by Andrew MacLellan

Intel is aiming its chips and Flash Data Integrator (FDI) software at the cellular phone market, and according to one source, already has some European phone makers prepared to swap out EEPROM in favor of the new boot block chip, which could save an estimated $1 to $4 in bill of materials costs per device.

"As the leader in flash memory, we take on the responsibility for creating new markets, and as such we have to help our customers develop tools. That's critical to our relationship," said Bill Howe, an Intel VP and GM of the company's Memory Components division, in an interview with Electronic News. "FDI helps our customers develop a more cost-effective solution more quickly."

In a typical cellular phone application, the memory subsystem consists of a flash IC for program code storage, SRAM for temporary data storage, and 64 kilobits of EEPROM, which is used for permanent storage of data such as system parameters and frequently used numbers. EEPROM is several times more costly per bit than flash, ships in lower densities and, with a longer programming time, consumes more battery life than an integrated flash method, according to Intel.

With no added circuitry, Intel said the new boot block flash architecture with FDI will eliminate EEPROM by partitioning both code and data on a single flash IC using 16 kilobytes of software code. The chip is divided into eight 8KB data blocks, with the remainder of the memory array split into 64KB blocks. The precise division of code and data is up to the OEM.

Intel said its FDI software emulates EEPROM-like byte write/erase by placing new data in separate flash blocks until a block is full, at which point the current data is moved to a new block, while the old block is erased.

FDI manages the flash chip using the system microcontroller, which stands idle up to 70 percent of the time in a GSM phone application, according to Intel. Software assist does not interfere with parallel operations, allowing write-suspend to the flash when the controller is called upon to execute code.

SGS-Thomson Microelectronics (STM), the leader in EEPROM sales last year, according to market research company Integrated Circuit Engineering (ICE), said cell phone makers are eager for any memory integration they can get, provided it maintains byte alterability, comparable endurance and performance, and assesses no die size penalty.

"SGS-Thomson supports the idea of a monolithic flash and an E-squared approach, and in fact we are developing a product with just this functionality which is sampling now," said Mark Mangin, memory marketing manager for STM's Memory Products group. "We're combining 4M of flash with 256K of parallel E-squared, and we support this idea. Where we differ is the implementation.

"Our products have a true, separate E-squared block in there, and I think there are some advantages to that compared to a software emulation."

The new Intel architecture, which also includes a power recovery feature, will be introduced in 4-, 8- and 16-megabit densities. Packaging options include a 48-lead TSOP and a 48-bump microBGA, which entails a 75 percent reduction in package size compared to the TSOP.

The 28F160B3-120 16M device is sampling now, with volume shipments scheduled for August. The device is priced at $20.50 in 10,000-unit lots in a TSOP package and at $22.50 in a microBGA package in like quantities. The 8M and 4M chips will sample in July and 4Q97, respectively. The FDI developer's kit will be available in July in source code from Intel at no charge.