Busy Ambit: new product; IBM deal; $4M In orders

Electronic News, April 21, 1997 by Judy Erkanat

Named BuildGates, Ambit's logic synthesis technology addresses the productivity bottleneck in high-performance, complex chip design. BuildGates' architecture employs a static timing analysis engine, automatic time budgeting and an advanced technology mapper to increase productivity without imposing fundamental change in design methodology.

Ambit said its new product reduces the time users spend in synthesis by at least 50 percent, besides producing improved quality of results. And, it offers a 5-7x overall capacity improvement over current synthesis methods, Ambit claimed. The tool automates methods for managing chip-level timing and is compatible with current design flows.

Featuring a TCL-based programmable user interface, BuildGates' modular architecture provides hierarchical synthesis with automatic constraint management. It also accommodates million-gate designs with minimal intervention and supports multiple, simultaneous delay calculators.

BuildGates' static timing analysis engine employs a pin-based timing algorithm which stores information at each pin in the netlist to enable incremental updates and automatic time budgeting across blocks. The incremental timing engine allows accurate exception characterization of false and multicycle paths and enables the chip-level analysis of million-gate designs in a short time.

With automatic time budgeting, BuildGates performs an intelligent allocation of delay across different levels of hierarchy. It also uses the standard TCL programming language for procedures and functions. Ambit also developed a algorithm-based technology mapping feature able to map to bigger cells without special pragmas or switches.

"The current synthesis technologies are targeted for mainstream design methodologies," said Prakash Bhalerao, president and CEO of Ambit. "When used on million-gate designs, they are time-consuming and difficult to use, generate inefficient results, and create extreme frustration for high-end designers. BuildGates eliminates these frustrations by giving users greater control over synthesis. Designers employing Ambit's product will realize significant productivity gains during the synthesis phase of the design cycle."

"Synopsys customers have to go 10-15 iterations, especially on timing-critical designs or those with over 100,000 gates," explained Venktesh N. Shukla, Ambit's VP, marketing and sales. "With our product, one synthesis run is enough, because BuildGates is linear and predictable."

Beta sites, 12 over the last five months, noticed a short learning curve and significant productivity improvements. One site synthesized modules with up to 100,000 gates, while another ran a top-level timing analysis on an 810,000-gate design in four minutes.

"Chromatic Research has evaluated three synthesis alternatives since its founding three years ago, and Ambit is the strongest contender so far," said Michael Klein, director of VLSI design at Chromatic Research. "We consider synthesis one of the key elements of our design flow that needs improvement because of the high performance and productivity needs, and large synthesized gate count (up to 500,000 gates) of our media processor designs. In our evaluation of BuildGates, we've seen up to 16 percent better timing on large blocks over our current design flow, which represents a very important advantage to our team. The tool has been quite stable, even as a beta release, and the support from Ambit has been outstanding, really taking ownership of our challenging design."

BuildGates is available immediately for use on SunOS and Solaris platforms. Support for other Unix platforms will follow later in 1997. The tool currently supports Verilog and will support VHDL in June. Pricing begins at $85,000. Those interested can meet BuildGates at the Ambit booth at the Design Automation Conference in June.

Ambit's agreement with IBM is to develop a design flow for high-performance, million-gate chips designs taking advantage of the emerging delay calculation system (DCS) standards. Ambit will work with IBM to ensure its libraries will support BuildGates' with DCL.

IBM also intends to provide libraries for BuildGates, starting with SA-12, its 0.25-micron/2.5-volt technology. The target delivery to mutual customers is 4Q97.

Ambit pulled in orders for BuildGates from Motorola, Toshiba, LSI Logic and Sun Microsystems, with a total value of more than $4 million.

"We've been impressed with the quality and consistency of the timing results produced by BuildGates," said Howard Landman, senior staff design engineer at Toshiba. "It seems to converge reliably on good solutions, even when given constraints that are too tight to meet. And that means one synthesis run is enough, we don't have to worry much about whether we're getting the fastest netlist the tool can deliver."

Dan Smith, Motorola's Firepower group director of engineering, agreed. "BuildGates is the closest thing to a plug-compatible synthesis tool you can get, and it consistently gave me improved performance results," he said. "It fit tightly into my existing flow, and I managed to learn the TCL interface within two hours."