New CPLD architecture solves traditional ISP problems

Electronic News, April 21, 1997 by Eric Pirpich

In-system-programming/re-programming (ISP/ISR), is the most recent of these features that allow logic changes to be implemented without removing the CPLD from the printed circuit board. This feature has proven especially beneficial in applications that dictate the use of fine lead pitch packages, such as TQFP. However, ISP/ISR only offers the ability to re-program a device--the ability make a design change without changing the device pin-out depends on the architecture and its approach to logic allocation.

Some CPLD vendors offer a common tip for re-fitting designs under fixed pin-out constraints and that is to never utilize more than 70- to 80 percent of the device's macrocells and I/O pins. Another way in which architecture limits are addressed is through package migration paths.

Before ISP/ISR became popular, many CPLD suppliers realized the routing/fitting problems in their devices. As a solution, they chose to offer multiple device densities in the same package type. The problem with these approaches is that designers must implement a much denser device than actually required by the design, so that pinout can be maintained when a design change is made.

Because of time-to-market pressures, designers have accepted this. In many applications, however, even over-purchase of silicon is no guarantee that a design change can be re-fit while maintaining a fixed pin-out. This is especially true when the application dictates a specific package size and/or type.

Architectures that exhibit the most problems in this area are those that rely solely on product term (PT) steering mechanisms such as logic allocators, PT allocators and expanders. Use of these mechanisms has been shown to reduce effective device density and cause routing problems. This occurs most frequently when making changes, under fixed pin-out constraints, to an existing design that utilizes a high (greater than 70 percent) percentage of the CPLD's key resources--macrocells and I/O pins.

Unfortunately for designers, such conditions are becoming the norm. This is compounded by shorter development cycles in which designs are validated by iterative testing and device re-programming rather than through pre-prototype simulation. ISP/ISR offers a substantial benefit under these conditions, but only to the degree that a CPLD's architecture can support design changes under fixed pin-out constraints.

One approach to solving this problem modifies the PT steering mechanism. The new PT allocator can re-direct logic from any macrocell to any other macrocell in the logic block. This approach has a fairly serious drawback though--it causes a variance in the predictable timing designers expect from a CPLD. The PT steering delay can vary greatly and be substantial, since it now depends on the distance between the macrocells in the logic block.

Even though this approach appears to be better for maintaining fixed-pinouts, it has also been shown to have limitations when a design change involves complex logic or high-utilization of the CPLD's macrocells and I/O pins.

Since the CPLD architecture's method of logic allocation is a major reason that problems can occur when trying to re-fit a design change, a substantially different approach is warranted to make ISP/ISR more useful for designers. Because the problem is traceable to the use of PT steering mechanisms, the new approach should eliminate these mechanisms. The issue with this idea, however, is that some high-speed means of supporting wide logic fan-in is required by today's applications.

An obvious solution is to provide a large number of dedicated PTs for every macrocell. Clearly, such an approach solves the problem if enough PTs are available. But how many PT's are enough? Since today's embedded processor architectures are dominated by 16- and 32-bit busses, a good first guess is 16-32. But providing 16-32 dedicated PTs for each macrocell in the CPLD would cause the CPLD to cost too much for many of the applications in which it is used today.

All About Architecture

A better solution provides a small number of dedicated PTs for each macrocell, and a separate pool of additional PTs accessible by all macrocells in the logic block. A new CPLD architecture offers this by combining the traditional PAL structure with the PLA structure. In this architecture, PT steering mechanisms have been eliminated from the PAL and five dedicated PTs are made available to each macrocell. In addition, a pool of 32 PTs is accessible to any or all of the macrocells in the logic block through the PLA. Because the PLA is in parallel with the PAL, the delay associated with it is minimal (about 2 nanoseconds).

The result is an architecture which enhances ISP/ISR use, since it accommodates design changes under high logic utilization and fixed-pinout constraints much better than architectures that use PT steering. Any logic change made in the PLA will not impact pin-out, since all these PTs are equally accessible by macrocells in the logic block. Complex (wide fan-in) logic functions can be implemented efficiently and without reducing macrocell density because the PLA offers a potentially large number of additional PTs for each macrocell.