Hybrid FPGAs will enable IP integration

Electronic News, April 21, 1997 by Thomas J. Hickey

As the density of field-programmable gate arrays has increased to more than 40,000 usable gates, designers have begun using these devices for more complex designs, because of their flexibility and time-to-market advantages. Many of these designs could formerly only be implemented in application specific integrated circuits (ASICs)--which also included standardized functions as pre-designed macrocells, or cores, incorporated in the array.

Designers continuously implement many of the same standardized functions in different designs. Some of these are proprietary to a particular design, but many are used by a wide range of manufacturers in a variety of end systems. Reusable functions have been implemented in soft cores--macrocells created in Hardware Description Languages (HDL)--because the cores are then portable and can be conveniently reused in multiple designs.

But certain functions are difficult to implement in programmable logic with HDL cores either because the standard functions specifications are beyond what is possible in an FPGA--such as a 66MHz PCI bus interface with its stringent I/O requirements--or is too big, such as a large segmentation-and-reassembly (SAR) function along with its necessary FIFO. Another reason might be it simply can't be implemented in an FPGA, such as an analog function.

Even when an OEM buys standard functions as an HDL core from a third party intellectual property provider, frequently the HDL code must still be extensively modified to target the specific FPGA architecture, in order for the target FPGA to perform the desired function at the required speed. Many of these functions can be integrated more cost-effectively and with better performance as hardware blocks of mask-programmable logic inside a programmable device.

Some of these functions are used so commonly that the volumes are high enough to make them economically feasible for use with FPGAs. Consequently, silicon suppliers such as Actel and Lucent Technologies are beginning to develop architectures that mix programmable cells along with hard-wired, mask-programmable cells, on the same chip. This results in a hybrid, or mixed, architecture that Lucent calls field programmable system chips (FPSCs).

System-level ASIC technology is used for the well-defined, industry-standard parts of the design. This is integrated with programmable logic for user-defined portions of the design--all on the same chip. Such integration also increases speed and decreases cost, while reducing power consumption and board space.

Two areas where FPSCs are especially in demand are the PCI bus--which is spreading across a wide number of industries--and in telecommunications and data communications applications, such as asynchronous transfer mode (ATM), where standards for many functions have already been set.

FPSCs can provide ASBs for a number of these commonly-used functions. The PCI bus, for example, is now used in network servers and telecommunications switches as well as in personal computers. An increasing number of chips, such as the most popular ATM SAR device, include a PCI bus. Instead of coming up with a bus standard for a particular design, the design engineer can use FPSCs that incorporate the PCI bus interface as built-in ASBs that will talk to a standard bus. Universal Serial Bus (USB) interfaces are also becoming more widely used, and are candidates for ASBs.

A number of functions in telecommunications and data communications applications are purely analog. In the ASIC world, most devices are largely digital chips incorporating a few specific analog function blocks. But FPGAs are completely digital--there are no analog FPGAs. Consequently, analog functions have been impossible to implement in programmable logic. With the use of FPSCs, however, this problem is overcome. An FPSC with a 155MHz SONET clock and data recovery ASB on it can receive 155 Mbits on an analog signal, extract clock and recover data from it, and convert it into a digital signal, eliminating the need for an extra line interface chip on the board.

Other communications functions that can be implemented as ASBs include a UTOPIA-2 interface, an ATM physical layer framer interface, an ATM SAR, a 100Mps fast Ethernet physical layer interface, and a quad/octal media access controller.

The PCI bus ASB is an example of FPSC solutions that were previously not possible on a programmable device. The 66MHz PCI specification is difficult enough to implement in ASICs, and impossible to meet in programmable devices. FPGAs are currently capable of implementing 33MHz PCI, but simply haven't had the I/O capabilities required by the 66MHz specification. With this new merged ASIC and FPGA architecture, designers can focus on implementing their own intellectual property in programmable logic.

Standards tend to emerge by trial and error over time. Consequently, a function that was implemented in programmable logic as an emerging standard, may tomorrow be a clearly defined and understood standard function. The standard portion can be hard coded in silicon and incremental logic implemented in programmable silicon. For this reason, what was once a reason for using an FPGA may tomorrow be the reason for using an FPSC.