Design-specific CPLDs key to utilizing ISR

Electronic News, April 21, 1997 by Norman Taffe

The ability to make design changes in the field or during board debug requires a further capability, in-system reprogrammability (ISR). This implies that the user's design changes won't modify the pinout of the device--a common problem with ISP CPLDs. Another point, often overlooked, is that ISR devices must also support design changes while maintaining critical timing paths. Only CPLD architectures that are specifically designed to allow design changes without pinout or timing changes can bring the advantages of field upgrades and rapid hardware debugging to programmable logic users.

ISP is not ISR

ISP is the capability to program a CPLD after the device is soldered on the circuit board--usually through a simple serial interface. In most devices, the serial interface conforms to the 4-pin JTAG interface standard (IEEE 1149.1). This allows devices from multiple vendors to be connected in the same daisy chain for programming and/or testing. Vendors typically supply software that supports programming from a PC (via cable from the parallel or serial port), as well as examples of the programming using standard Automatic Test Equipment (ATE) or on-board microcontrollers.

Unfortunately, providing the silicon interface and software to support in-system programming is not all that is necessary to provide in-system reprogramming. In practice, very minor design changes to many ISP CPLDs can cause pinout and/or timing changes. Changes in either pinout or critical timing paths mean that the design will not function without rewiring the board--the very thing that in-system reprogrammability seeks to avoid. The reason for these problems is related to CPLD architecture. To provide the capability of on-board design changes, a CPLD architecture must be designed with ISR in mind.

Architecture is Key

To support ISR a CPLD architecture must be designed to support design changes without pinout changes. This requires the ability to easily accommodate a wide range of routing options in the global interconnect and between individual logic blocks. Many CPLD architectures suffer from limited interconnect resources and such resources are used to connect each I/O pin and macrocell feedback from the CPLD logic blocks throughout the device. As a result of this limitation, a design's fit is tightly tied to a particular pinout--often as originally selected by the development software. When the pinout is fixed during board layout, subsequent design changes often fail to fit due to routing limitations within the device. One way to solve this problem is by providing multiple chances for each signal to route to each logic block and include redundant input paths into each block.

Another issue impacting the ability to support ISR is the flexibility to shift product-term resources as needed for design changes. In many cases, a design change will require additional product term resources relative to the original design. In most CPLD architectures these additional product terms are moved in groups of four or five from neighboring macrocells and cannot be shared across multiple outputs. This type of architecture limits the flexibility of the software to support design changes in the same pinout.

An often overlooked aspect of ISR is the need for predictable and consistent performance. A design change that results in performance degradation can be just as fatal to field upgrades as a brand new pinout. Again, a CPLD architecture can be designed to avoid this pitfall.

To provide predictable timing, a CPLD must support uniform delays for all signals regardless of resource utilization. In most CPLD architectures, the delay for a particular signal is dependent on a variety of factors, including the number of product terms used, signal fanout, which I/O pins are used, and the type of interconnect traversed. This variability means that changes to a design will often cause changes to the timing of particular signals because the same resources may not be used once the change is made.

Conversely, a fixed, simple timing model assures that added delays won't derail design changes. This means that the signal delay is independent of the path to which it is mapped. This requires an architecture where all of the signals traverse identical paths and there is no penalty for utilizing more or less resources. The user benefits not only from ISR support, but also from a much easier design process.

ISR Advantages

ISR increases engineering productivity during hardware development. The productivity increase stems from faster debug cycle times. In one particular application, there are multiple approaches to hardware implementation that have various impacts on system performance. Instead of socketing and repeatedly reprogramming fragile TQFP devices, or building up separate prototypes for each implementation, this engineer uses the ISR capability of a CPLD to evaluate different hardware implementations in real-time. With his PC connected directly to his circuit board, the engineer evaluates the different options by simply editing the VHDL source code, synthesizing and reprogramming right from his PC. There are no expensive programmers to buy or sockets to worry about. The engineer has the confidence that these modifications can be made without affecting pinouts or performance.