Flash-based FPGAs target ASIC design environment

Electronic News, April 21, 1997 by Todd Scott

In 1996, the gate array and cell-based application specific integrated circuit (ASIC) market grew to a combined $13 billion while gate counts and non-recurring engineering (NRE) fees soared to new levels. As a result, more ASIC designers are considering high density field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs) to eliminate expensive design iterations and to mitigate schedule risk before committing to high volume ASICs.

Unfortunately for the ASIC designer, these products are designed as extensions of programmable logic devices (PLDs), not as ASIC products. The ASIC designer venturing into reprogrammable gate arrays for prototyping wants to remain in the familiar and more advanced ASIC design environment--an environment proven with million-gate designs. In addition, the designer does not have time to deal with the additional chip design, system design and security issues that come with volatile PLDs.

Flash-based FPGAs, based on ProASIC (Programmable ASIC) technology, are engineered to provide the ASIC designer with the reprogrammable ASIC solutions for design verification and rapid prototyping, prior to committing to the NRE expense of a high volume ASIC. The technology features a standard ASIC design environment, reprogrammability, non-volatility, and a cost/performance comparable to SRAM-based FPGAs.

Although SRAM-based vendors may have a "backdoor" to ASIC design environments, used gate count and performance suffer drastically when that backdoor is used. These devices require proprietary design environments to achieve the levels of utilization and performance that flash-based reprogrammable ASICs achieve using standard ASIC design environments.

Rather than provide the traditional FPGA/CPLD backdoor approach to accessing ASIC design tools, flash-based devices are designed to work seamlessly within an ASIC design environment. This is accomplished through the concurrent engineering of library design, circuit design and chip architecture with the flash memory process.

For the ASIC designer, working in a known and proven design environment eliminates the learning curve associated with FPGA/CPLD design environments. The FPGA/CPLD architectural mapping step is eliminated resulting in a streamlined design flow propelling the product to market much faster.

Existing customer intellectual property (IP) is targeted to the prototype by virtue of common HDL practices. Moreover, IP created for the prototype is quickly ported to the ASIC for high volume production. The ability to directly retarget HDL (and the design scripts developed during prototyping) to ASICs provides the fastest path to high volume without the need to use specialized design conversion houses.

Flash Utilizes ASIC

Attributes

Flash FPGAs use a high-density flash CMOS process with selected ASIC attributes. The flash process provides the basis for re-programmability and the ever important non-volatility. With the intrinsic CMOS process, high performance and gate array functionality are easily accommodated. The programmable CMOS cell in the array has three-inputs and an output. This is very comparable to the basic cell in a CMOS gate array--a two-input, one-output device.

The programmable cell may be configured as a two-input NAND gate, a three-input MUX, a distributed memory element or a full D-type flip-flop. In addition, the flash FPGA cell does not have the dedicated flip-flops or look-up tables (LUTs) found in SRAM-based products. This is a critical factor in ensuring design compatibility with gate arrays.

The technology boasts a programmable interconnect switch that is seven times smaller than SRAM-based switches. This enables a highly efficient hierarchical interconnect capability which further resembles ASIC technology.

Traditional FPGAs (antifuse- or SRAM-based) provide either non-volatility or reprogrammability. Flash-based FPGAs provide both non-volatility and reprogrammability in a single device. Non-volatility--through the flash memory--provides program retention, IP security, fewer devices, higher reliability, simplified system design and accelerated board conversions to high volume ASICs. As a result, once programmed, the devices are treated by the design engineer as though it were a true gate arrays. There is no need to hassle with the program bearing companion chips required by SRAM-based FPGAs, nor is there need to worry about their IP security issues.

Reprogrammability enables design iterations without additional component purchases or board rework and facilitates rapid adoption of evolving system standards. Changing encrypted access codes in the field is also possible and secure.

Smaller Die

Flash memory processes tend to have several more processing steps than standard CMOS processes used for SRAM-based FPGAs/CPLDs. As a result, if die sizes were equivalent, flash devices might cost slightly more. However, die sizes are not equivalent. In fact, design techniques combined with flash memory process attributes have enabled these FPGAS to be significantly smaller than SRAM-based CMOS products.