Metal-layer antifuse FPGAs are engineered to perform

Electronic News, April 21, 1997 by John Birkner

The antifuse concept realizes the systems designers dream of having an off-the-shelf, standard component application specific integrated circuit (ASIC) that is ready-to-use in every respect, except for the last step of customizing the metal wire interconnect that is unique to the designers application. Here the interconnect is the value-added intellectual property (IP) that differentiates the designers product from the competition. Also, this interconnect is where the designer needs the best tools for developing, debugging, exploring and optimizing a design.

Sea-Of-Logic Cells

Simply stated, the metal-layer antifuse FPGA is a sea-of-logic-cells covered by a matrix of wire segments and programmable links. The blank FPGA arrives from the silicon manufacturer with the antifuse programmable links in the normally open state. The designer configures the FPGA on site, using a device programmer that connects the antifuse links, transforming the blank matrix of wire segments into routed nets, connecting the logic cells to implement a desired function.

Antifuse links in metal-layer FPGAs are small, limited only by the metal pitch of the silicon process, allowing extravagant use in connecting abundant wire segments arranged in horizontal and vertical tracks afforded by three-layer metal technology. The abundance of interconnect provides optimally routed, low resistance nets required for high speed logic designs. Using the first layer metal to form the basic logic cell, antifuse interconnect can be placed above the logic cell transistors in locations at every intersection of second and third layer metal, forming an orthogonal grid of segmented tracks. Compared with FPGAs using two-layer metal technology, a two-to-one die size reduction is obtained by placing the interconnect above the logic.

SRAM-based FPGAs use transistor pass gates to form networks that interconnect logic cells. The networks are specified by SRAM bits that are loaded on power-up and that may optionally be reconfigured. Advantages of this approach include the convenience of debugging prototypes by downloading code revisions directly, the ability to upgrade engineering changes in the field and the ability to reconfigure on the fly. However, SRAM-based FPGAs can't afford the die sizes required for abundant routing tracks, just as they can't afford fully populated interconnect. Consequently, SRAM-based FPGA designs often result in long compile times, manual routing of critical paths, low logic cell utilization, pin-out changes and timing instability through design iterations.

In addition, with the advances in process technology, migration to deep submicron architectures is not limited by metal-layer antifuse technology either.

I Have a Vision

The vision of antifuse FPGA engineers is to provide a programmable ASIC that matches the performance, density, cost and tool design flow of a masked ASIC. This vision is close at hand in sub-20,000 gate densities, especially in pad limited designs.

The wealth of routing resources in antifuse FPGAs relieves the heavy burden that otherwise strangles place and route software tools in hooking up a netlist exported from an HDL synthesis design flow. Place and route execution times are measured in minutes, rather than hours or days, giving the designer shorter time-to-design and a better result afforded by more design-spins, increased cycles of learning and design exploration.

Place and route tools for antifuse FPGAs are automatic. When routing resources are abundant, fast simulated-annealing placement algorithms easily choose logic cell locations according to the designers' critical timing constraints. Routing the logic cells with interconnect networks is then a simple task. When routing resources are scarce, as in the case of SRAM-based FPGAs, placement algorithms can bog down with numerous cycles of place and route retries. Furthermore, when place and route tools fail to complete, handcrafting is required.

Antifuse Pin-Locking

Pin-locking is a standard procedure for antifuse FPGAs. This allows logic design-spins free of printed circuit board (PCB)-spins, resulting schedule delays. Pin-out maintainability is critical when logic design changes are made after the PCB has been fabricated. Changes made to the logic design may result in a new pin-out for FPGAs that have limited routing resources. The new pin-out requires a change to the PCB and results in additional schedule delay. Metal-layer antifuse FPGAs hold pin-outs through multiple design-spins. Some designers take advantage of this stability through design iterations by employing concurrent board development.

Antifuse FPGAs are secure as well. Designers' intellectual property code is buried inside the antifuse of the device programmed with non-traceable data patterns in the same manner as metal interconnect of masked ASICs. The designer's proprietary trade secrets are safe, compared to SRAM-based FPGAs where the code can be viewed when loaded from EPROM or RAM during initialization.