CPLDs drive easy-to-use software, hardware exploitation

Electronic News, April 21, 1997 by Mike Cho

User-friendly hardware solutions are built into a chip's architecture for users to exploit. These hardware solutions include fixed timing for guaranteed performance, in-system programmable (ISP) CPLDs compatible with the Joint Test Action Group (JTAG) standard (IEEE 1149.1), and Peripheral Component Interconnect (PCI) bus standard compliance. These hardware solutions also include 100 percent routability and pin-retention, multiple power modes and supply voltages for low-power usage, and multiple packages. The overall benefits for users are faster time-to-market, greater flexibility in design, and flexibility in manufacturing and maintenance.

For design software, CPLD users want inexpensive, easy-to-use graphical user interface (GUI)-oriented tools on PC or workstation platforms. In addition to good on-line help and documentation, the tools must accept mixed-level design entries such as schematic capture, VHDL and ABEL. These software tools must also be available through third-party vendors so that the users can design on a familiar platform.

For fitting software, the users want easy and fast device selection, fitting, placement, routing and JEDEC creation. Widely available macros in libraries, interactive fitting schemes, and user-friendly reporting structures enhance ease of use. Easy-to-use fitting software should achieve high device utilization by taking advantage of a chip's architecture, should have a high percentage of first time fit, and should run fast in fitting a design.

As CPLDs increase in density, simulation I/Os and performance users require more complete and accurate behavioral and timing simulations to handle increasing device complexity. Often systems designers want easy ways to integrate CPLDs into board-level simulation. This requires high-level design back-annotation and Verilog models. When combined with spice and IBIS models, designers obtain more complete simulation results before starting volume production.

Architectural Exploitation

CPLD architectures play one of the most critical roles in making hardware easy to use and easy to exploit with software. Most CPLD vendors offer products built on a type of multiplexer-based central switch matrix architecture. Through fitting software this allows designers to achieve faster fit, 100 percent routability and device utilization. Also, through inherent architectural strengths many CPLDs retain pinouts after design changes and refits. This pin-retention or pin-locking feature is critical for users not only to retain the pinouts but also to maintain the expected timing, especially as CPLD densities increase.

To alleviate the concern for variable timing, CPLD vendors offer guaranteed fixed timing on many products. For these products, regardless of product-term loading or interconnect routing, device speed performance is maintained before or after design changes. Fast fixed timing is especially critical in PCI designs.

PCI Compliant Products

Currently, virtually all CPLD vendors now offer ISP products as standards. As an additional improvement, many ISP products are now programmable on-board using the JTAG boundary-scan standard (IEEE 1149.1). Both JTAG and non-JTAG compliant ISP products offer fewer manufacturing process steps, higher quality and reliability, lower design cost, and faster time-to-market. The JTAG standard, widely used to test printed circuit boards, enhances the ISP feature by providing automatic test equipment with JTAG interfaces to test CPLDs for connectivity as well as programmability.

This can also be said for the PCI local bus standard. For users' PCI bus designs, today's CPLDs meet the AC, DC and protocol requirements at guaranteed pin-to-pin delays of 12 nanoseconds or less. When considering new sub-micron processes that deliver faster speeds at higher densities, PCI compliance can add more flexibility to high bandwidth and data intensive designs.

Newer and finer-geometry semiconductor process technologies have also introduced low-power products such as microprocessors and memories. This low-power product offering and usage trend has spread to CPLDs and is continuing. CPLD users now expect at least 3-V/5-V mixed voltage safe I/Os. Within the 5V supply voltage segments, many vendors offer products with at least two programmable power modes. Also, many vendors now offer chips at various densities running at 3V or 5V supply voltages. Flexibility in power management adds ease of use to systems designers.

Diversity in packages provides added freedom to CPLD users, who must think through the design, manufacturing and maintenance phases of their products. With packages increasing in pin counts and fragility, users in the past have demanded safer reprogrammability. This resulted in ISP. Now as CPLD density climbs to 512 macrocells, in addition to PQFP and TQFP, new products are rolling out in BGA packages. The electrical properties of these packages are relevant in performing timing or behavioral simulations.

Thermal characteristics affect the device performance and reliability. With rising device density and power dissipation, CPLDs require packages with low thermal resistance. Some PQFPs use metal to ease in dissipating heat. The thinner the packages, the higher the thermal resistance. For reference purposes, thermal resistance values for typical PQFPs and TQFPs used for CPLDs range from 20 to 40 degrees per watt in typical systems applications. For BGA packages, typical thermal resistance values are 10 degrees per watt. In the manufacturing and maintenance phases of a product's life cycle, package choice has great implications in the device junction temperature and consequently the device's reliability over time.