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Electronic News, April 28, 1997 by Andrew MacLellan, Peter Brown

Like a tailor fitting clothes to the Incredible Shrinking Man, integrated circuit designers are compelled to deliver ever-lower voltage levels as they strive to keep pace with the seemingly inexhaustible demand for semiconductor miniaturization.

Particularly in the Japanese and Asian markets, where space is at a premium, wireless and portable applications, from cellular phones to emerging handheld PCs, are in a relentless drive to reduce form factor, extend battery life and lower cost, while promising a simultaneous improvement in performance.

Several engineers here at CICC will explore power supply issues in an effort to reduce semiconductor operating temperatures and power dissipation without impairing circuit performance.

Presenters from the University of Illinois at Urbana-Champaign will deliver a paper detailing a method for reducing gate-level power leakage to enable ultra-low-power CMOS circuits. The paper notes that power consumption threatens to compromise chip reliability in highly integrated VLSI designs while increasing circuit noise and requiring larger battery packs or reduced operating times.

Rather than lowering threshold voltages, which the University of Illinois team contends will increase power dissipation caused by sub-threshold conduction in the MOSFETs, a new method will be proposed. The technique involves a small amount of additional circuitry integrated during logic design to force a multi-gate logic device into a low-leakage state during idle periods.

The researchers claim to have developed an algorithm to determine a good low-leakage input vector which they say reduces power leakage by 54 percent when demonstrated on ISCAS-89 benchmark circuits.

Another University of Illinois paper expresses the need for CAD development tools capable of making high-level power estimation in order to predict nominal power dissipation using the Boolean equation as a functional view. According to the study, current single-output Boolean function-based modeling often underestimates the area, or gate count, of the chip. A new model, which will be outlined here at CICC, proposes improved area prediction to more accurately gauge total capacitance.

A paper coming from Toshiba proposes a new architecture claimed to scale down threshold and supply voltages without causing standby leakage current. Unlike multi-threshold or variable threshold voltage schemes, which require additional circuits and process steps, the paper introduces a new technique known as extended-CVS (ECVS).

This automated design technique uses two supply voltages and consists of structure synthesis, placement and routing. According to Toshiba, the structure synthesizer "clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced or the unreduced voltage, one to each row, so as to minimize the area overhead."

With no performance degradation, the approach is claimed to have reduced power by an average of 47 percent when applied to the random logic modules of a media processor, with an area overhead of 15 percent at the random logic.

Intel Power Talk

Intel will deliver a paper here in an effort to better estimate power dissipation by minimizing uncertainties in primary input specifications. According to Intel, power dissipation may be accurately estimated only when the exact probability and activity of the primary inputs is known, values for which may not be readily available. The report seeks to define a measure of power sensitivity to primary inputs and present new algorithms to estimate such variances in large CMOS circuits.

Papers covering radio frequency (RF) ICs and ASICs will target wireless applications and common problems involved in their design and implementation.

As system-on-a-chip technology becomes reality, ASIC vendors are beginning to incorporate multiple peripherals on-chip. Many of these system ASICs have already found a home in the wireless arena, although they include a range of other applications as well.

Belgium-based IMEC will present its direct sequence spread spectrum (DSSS) ASIC that the company claims contains all the digital functions necessary for an L-band satellite pager. Using VLSI Technology's VSC653 standard-cell ASIC, the device integrates an ARM6 core, dual-port SRAM memory, UART and flexible DSP hardware to achieve full programmability. IMEC claims the system-on-a-chip would reduce the number of components used in traditional methods while resulting in a 45 percent power savings.

Toshiba, meanwhile, will showcase changes within ASIC-based fully-balanced analog system design upon the emergence of mixed-signal capabilities. Toshiba will tackle the increasing trend toward merging mixed digital and analog parts while maintaining a balanced low-noise system. The company said its paper will prove that any technology--CMOS, bipolar, BiCMOS or GaAs--can be easily and effectively converted from a single-ended system to a balanced, double-ended mixed-signal system.