Xilinx, IDT boundary scan issue surfaces

Electronic News, April 28, 1997 by Peter Brown

The memo states that "any parts that we (Xilinx) have with boundary-scan on them are in violation of U.S. Patent 4,710,927 entitled 'Diagnostic Circuit,' " a patent that is held by IDT. In addition, the patent in question includes the use of a coupling mechanism between input pins and a command register, the input pins and a data register and the output of either of those registers and the output pin, the memo said.

Isabelle McAndrews, patent attorney for IDT, said she would not comment on a possible infringement on this patent by Xilinx, nor would she comment on whether IDT had approached other companies regarding this patent and possible violations. Xilinx would not comment on the issue.

However, according to programmable logic house Actel, IDT has an open invitation for a cross-license agreement for its full patent portfolio. David Van De Hey, VP and general counsel at Actel, said, "IDT and Actel are members of a group of semiconductor companies that monthly gets together and discusses patent and other issues. IDT has a standing offer to cross-license its patent portfolio to any of the group and every so often mentions they have this patent. Actel has not accepted this offer, but it is there if we want it."

Ms. McAndrews would not comment on whether any legal action has been taken regarding possible violations and would not give a time frame as to when, if ever, any legal action would be taken against Xilinx or any other company.

The engineer's memo states that "the patent appears to grant a rather broad claim to a serial communications mechanism that both provides and extracts information from a device using a 4-pin interface." Also, it states concerns about the consequences involving the numerous companies that utilize boundary scan, as well as Xilinx's interest in the IEEE's reaction. Boundary scan is a designed-in test technology which is codified in an IEEE standard.

IDT's U.S. patent 4,710,927--invented by Michael J. Miller and granted on Dec. 1, 1987--focuses on IC devices' built-in test facilities with serial diagnostics. IDT states in the patent that as the integration level of ICs has increased, so has the board-and system-level integration, and that trend has increased the difficulty of ensuring correct designs and facilitating production/field testing.

"The desirable higher packing density achieved with surface mounting (LCC) and tighter pin spacing have also contributed to more difficult testing conditions," the patent states. IDT said that many system, board and IC companies have started to implement built-in test facilities in their products to relieve the situation. Intel microprocessors, for instance, have boundary scan features built into them.

According to IDT's patent, the techniques for testing logic circuits are often inefficient and ineffective for testing sequential logic circuits. IDT asserts that if the values in all of the registers of a sequential circuit can be controlled and watched with a straighforward operation, the diagnostic tasks could be reduced for the combination circuit.

The technology presented in the patent claims to provide a diagnostic circuit which can employ test addresses and test commands as well as test data. The patent states an advantage to the technology "is the ability it affords to provide a diagnostic circuit which is suitable for inclusion in an integrated circuit device with minimum number of additional pins."

IDT's diagnostic circuit is said to employ a command register, a data register and a multiplexer. The command register integrates a clock input, a serial data input, a serial data output and a set of parallel data outputs. The data register includes a clock output, a data input for use with the clock output, a serial data output, a load input, a number of parallel data inputs and a number of parallel data outputs. The multiplexer features two date inputs and one data output.