Cadence's new verification plan

Electronic News, June 9, 1997 by Judy Erkanat

San Jose, Calif.--Cadence Design Systems is rolling out a new verification strategy this week at the Design Automation Conference in Anaheim, Calif. The first phase includes OMI-based links; productization of the Cobra cycle-based simulator; and integrated coverage analysis through an OEM agreement with TransEDA..

The new software links between Cadence's Alta system-level and hardware description language-based chip-level simulation tools are based on the Open Modeling Interface (OMI) standard specification from the Open Modeling Forum (OMF). This establishes a functional verification environment with a simulator-independent model interface to support functional modeling at multiple levels of abstraction. It also provides accurate test bench extraction from system models, and co-simulation of mix-and-match intellectual property (IP) blocks.

IP providers can package IP sources with the OMI interface layer in object form along with appropriate view ports to give necessary simulation information without revealing the IP source. Any IP model supporting the OMI interface can co-simulate with any simulator supporting OMI.

"It is now possible to evaluate the architectural performance of a DSP core with an abstract system model and then use the same system model to verify its RTL implementation through the OMI interface built into SPW and NC-Verilog," said Glenn Abood, VP and GM for Cadence's logic design and verification products. "Cadence provides the unifying technologies needed to verify the system specification all the way from architecture to gate level. This is the only way to guarantee that RTL meets system specifications."

Support for OMI will be available at no additional charge with Cadence's complete suite of simulators beginning 4Q97. It is available with Alta SPW and will be supported on all future Alta products.

The company will debut the Cobra cycle-based simulator at DAC. The product combines cycle simulation performance with the ability to co-simulate HDL and system models. Closely coupled to Cadence's NC-Verilog event-based simulator, Cobra was first developed at the Cadence Berkeley Labs and is currently in production use at customer sites.

With simulation performance equal to multi-million gate designs and 30-100x faster runtimes over event-driven simulators, Cobra is complemented with a service offering and Cadence's new high-level functional modeling group for transitioning to cycle-based verification.

Cobra provides sustainable, accelerated simulation performance on mixed behavioral-, register transfer- and gate-level designs. "We believe that cycle-based simulation is essential for verifying today's complex chips, and we're building our design methodology accordingly," said Jeremy Nichols, staff engineer at Unisys. "Cobra is a key component of that design methodology."

Cobra, available for volume shipments in December, runs on all Sun Solaris and Hewlett-Packard Unix-based platforms. It is list priced at $60,000 for a floating license.

TransEDA of the U.K. entered into a multi-year agreement with Cadence through which TransEDA's electronic design automation (EDA) software will be linked with Cadence's logic simulation software. This will produce an integrated profiling/simulation product.

Under terms of the OEM agreement, Cadence's Verilog- and VHDL-based simulators will be integrated with TransEDA's HDL code coverage tools known as VHDLCover for VHDL and VeriSure for Verilog HDL. The agreement expands the scope of the existing Connections Program partnership between the companies.

The bundled product will be available 3Q97 running on all Sun Solaris and HP Unix-based platforms. A product based on Windows NT will be introduced later in the year. VHDLCover and VeriSure are each priced at $15,000 for a floating license, and will be sold and supported with Cadence's Verilog-XL, NC-Verilog, Leapfrog and Cobra simulators.

These technology areas are supported by Cadence's new competency group focused on high-level functional modeling of IP, supporting model development kits and custom modeling services. Cadence's unifying verification strategy and roadmap shifts from an ASIC-out to system-in methodology for rapid creation of system-level models to verify specifications of functions and automatic leveraging of the same model to verify cycle-by-cycle interactions of implementations.