RIOS Systems notebooks to use OPTi Viper chipset

Electronic News, July 14, 1997

Powered by the Intel 120MHz Pentium Processor, the RIOS Sub-Notebook is a slim (1.26/32cm), lightweight (2.65lbs/1.2kg) sub-notebook computer with an 8.4-inch color TFT display. It uses the Viper-N/ 64-bit mobile chipset.

OPTi's market proven core logic silicon provides the perfect platform for implementing low-cost, high function sub-notebooks, asserted George Fang, VP of Asia Pacific sales at OPTi. This is a growing market in which OPTi will continue to lead. Y. Hosoya, GM for development at RIOS, commented: We selected OPTi's Viper-N/ core logic chipset as the optimized solution for our highly integrated, small form factor sub-notebooks. The RIOS Sub-Notebook is suitable for mobile applications with features such as an 8.4-inch color TFT (640x480 pixels), an IrDA/ASK infrared port, and three PC card slots to handle a variety of communication and storage options. The base memory configuration includes 8MB of RAM, which can be upgraded to a maximum of 40MB. It also includes a Card Bus/ZV port for video capture and teleconferencing applications, and 100-240 volts AC adapter for use anywhere in the world.

The OPTi Viper-N/ chipset is designed for PCI-based mobile applications. Viper-N/ features power management capability and is suitable for Intel Pentium 75/90/100/120 and Cyrix 6x86 processor based notebooks. The chipset incorporates desktop-like performance features such as L1 and L2 cache support, a 64-bit DRAM controller and an integrated PCI controller, in a three-chip set.

The Viper-N/ power management unit offers claimed minimum power consumption for extended battery life. For typical applications, the Viper-N/ power management unit is said by the company to reduce power consumption by as much as 80 percent.

A system without TTL is achievable with the chipset's synchronous cache. PCI offers upgradeability to standard interfaces such as PCMCIA/Card Bus and PCI docking stations. Viper-N/ also features an integrated local bus IDE controller to avoid ISA data bus bottlenecks.