Role of embedded DSP tech growing in consumer arena

Electronic News, August 18, 1997 by Rob Woudsma

It is widely recognized that a growing number of high-volume digital IC products are enabled by the use of embedded processor technology. The degree of integration in the deep sub-micron era enables complete systems-on-a-chip. Such integrated systems are assembled from a set of ASIC building blocks, like processor cores, embedded memories, and peripherals. The immediate availability of ASIC module libraries strongly contributes to time-to-market performance and the composition of new chip architectures. The application of embedded processor cores inherently yields high functional flexibility by modifying on-chip program memories of either ROM-type (mask-programmable) or RAM-type (downloadable).

With the advent of these new fabrication and advanced ASIC technologies, the number of completely new consumer applications has grown substantially. Well-known examples include digital telecom terminals, PC multimedia and new digital audio/video functions. To a large extent, these applications depend on the development and industrial availability of efficient embedded DSP technology.

As compared to general-purpose, stand-alone DSPs introduced in the 1980s, effective embedded DSP technology is characterized by a combination of a high functional performance, an efficient chip area usage and a high degree of configurability. For portable applications, low-power operation is essential. These characteristics are quite obvious while observing the key design constraints for high-volume, consumer-centric embedded applications: low cost, short time-to-market and low-power operation. In this context, it is crucial to focus on functional performance per unit cost (chip area or power consumption), rather than raw clock speed or MIPS performance. Simply boosting DSP speed performance would result in fast execution of typical DSP functions like filter or transform algorithms, but this could implicitly involve severe area and/or supply current penalties.

It is often more appropriate to start with a thorough analysis of the target application domain, and tune the DSP architecture to achieve an optimal balance between specific application requirements and the native DSP property of reprogrammability. Examples of this approach are the Philips-based KISS architecture, originally designed for telecom baseband processing applications, and the EPICS flexible DSP architecture. The EPICS DSP architecture, an example of a highly customizable embedded DSP architecture, has already been reported. The EPICS approach has shown that customization is feasible and advantageous for a number of high-volume IC products. Customization has been applied in terms of instruction-set coloring, selection of dedicated peripherals and word-length parameterization. Data word lengths in the range of 12, 16, 18, 20 and 24 bits have been selected in different variants of EPICS DSP cores, depending on the target application domain being served.

Some of these word-length settings cannot be found among existing "general-purpose" DSP cores, which focus on either 16x16 or 24x24 bit. Instruction word length also turns out to be a beneficial result of parameterization, and 24-, 28- and 32-bit instruction-set architectures have been applied, depending on the required level of SIMD parallelism and the need for orthogonal instruction coding. Concrete EPICS product applications are in the areas of cordless phone (DECT) and car audio (CarDSP). In these IC products, the EPICS DSP core is a key component that is integrated with other system components such as system controllers, embedded memory modules and analog peripherals.

REAL DSP

EPICS and KISS methodologies have been the basis of the development of the next-generation DSP architecture, known as reconfigurable embedded DSP architecture for low-cost and low-power applications (REAL DSP). The REAL architecture incorporates several key technologies from EPICS and KISS to create a new DSP solution. The REAL DSP family is a fixed-point dual-Harvard architecture. Its first members are 16-bit DSP core variants, offering different levels of parallelism in the datapath at associated hardware cost. On top of a single-cycle, pipelined multiply-accumulate, the datapath features a set of arithmetic and logic operations, barrel shifting, bit manipulation and saturation/rounding. A large variety of addressing modes, including bit reversal, is offered by a pair of address-calculations units. Control features include multiple interrupt lines, hardware loop control and nested subroutines.

For complex, irregular functions running on a DSP, an orthogonal instruction set such as EPICS is too costly in terms of program storage. This is addressed by a more compact instruction code incorporated by REAL DSP, which increases parallel processing power at the architecture level by having more functional units and instruction pipelines. The EPICS generation performs well for specific individual applications, where customization is a concrete target. There is a growing class of embedded applications, however, where different functions with diverging architecture requirements have to share the same DSP platform. For these applications, the REAL DSP core behaves in a general-purpose manner without affecting the advantages of efficient area and power usage.