UTSi technology proves its mettle in CMOS applications

Electronic News, Oct 13, 1997 by Ron Reedy

UTSi technology is a silicon-on-insulator (SOI) CMOS process with proven manufacturability for high-performance, low-power commercial CMOS applications. UTSi CMOS is currently in production at Asahi Kasei Microsystems Co. Ltd. (AKM), Tokyo, Japan, in a 0.7-micron poly, triple-metal process.

Using the single solid-phase epitaxy (SSPE) regrowth technique, a high-quality ultrathin-silicon (UTSi) film is formed on a man-made sapphire substrate. This process yields a low-defect-density silicon film with a final thickness of 100 nanometers and electron and hole mobilities similar to those found in bulk silicon. The resulting UTSi wafers are then processed with standard CMOS processing equipment. The process uses LOCOS for isolation, 12nm gate oxide, 0.7-micron minimum drawn gate, LDD drain engineering using oxide spacers and aluminum metallization with MoSi2 barrier metals and SOG planarization.

The transparency of sapphire can cause optical sensors in wafer handlers to have problems detecting wafers. Therefore, a polysilicon/nitride sandwich is deposited on the back side of the wafer. This allows standard wafer handling equipment to be used. Due to the higher thermal expansion coefficient of sapphire (approximately twice that of silicon), simple precautions must be taken during high-temperature steps to avoid wafer breakage. Diffusion tube push and pull temperatures are decreased and elephant-trunk enclosures are used at furnace tube entrances to slow the cooling of the wafers when they are pulled from the tubes. Otherwise, the UTSi process flow is industry-standard. In fact, elimination of wells and certain isolation-masking steps actually lower the cost of the manufacturing process as compared to the standard bulk-CMOS process.

Low Defect Density,

Low Leakage

Detailed statistical analyses are available for two devices currently being manufactured using the UTSi process: 1) a high-performance dual fractional-N RF-1.1GHz, IF-510MHz PLL (1.5K gates) and 2) a low-power digital shift register (100K gates). The results show a measured defect density for both products of between 0.65 and 1.04 defects per square centimeter. This demonstrates the capability of running high-performance RF analog and large digital products with yields comparable to bulk processes.

The excellent leakage-current characteristics of UTSi transistors make UTSi an ideal process for super-low-voltage applications. Iddq measurements from a 100K-gate shift register manufactured in the process show a median value of 4.25 micro-angstroms. These features will allow dramatic savings in power consumption in both standby and active operation for the digital systems of wireless communication products.

Industry-Standard

Qualification

High-temperature operating life (HTOL) analysis was performed on a 1.1GHz phase-locked-loop. Conditions were 125 degrees C ambient, 3.6V for 2,000 hours in a plastic package. With no fails, the sample size resulted in a failure rate calculated as less than 5 FIT.

Comparing experimental ring oscillator delay data from the existing-production and next-generation 0.5-micron UTSi CMOS processes against data published for 0.5-micron and 0.25-micron Leff bulk processes, the literature shows performance improvement of one to two technology generations over bulk silicon CMOS. USTi devices also exhibit high linearity at very low current, making the technology useful for image-rejection mixers and other applications that high third-order intercept (IP3) points, including CDMA RF receivers. RF characterization data shows 32GHz Fmax performance on a 0.7-micron drawn transistor and 64GHz Fmax performance on a 0.5-micron transistor. The UTSi process reduces single-transistor latch and breakdown effects.

Capability Demonstrated

UTSi has demonstrated the capability of yielding FD MOSFETs with small Vth variation. It is believed that the low Vth variation seen in the UTSi process is due to the low segregation coefficient of boron into sapphire, as well as the extreme uniformity in epi thickness. The process control of Vth, as well as gate oxide thickness and Leff on short channel devices, is similar to bulk CMOS processes. Gate oxide BVOX results show that the defectivity and quality of the gate oxide make the process suitable for VLSI applications.

The UTSi CMOS process is compatible with standard CMOS processing equipment and techniques. Process parameters show excellent control and the process has demonstrated high reliability. Transistor and device parametric performance show that the technology is ideal for low-power wireless semiconductor applications. Detailed results may be obtained from Peregrine Semiconductor Corp. in San Diego.