S3 breaks ground by using own DRAM

Electronic News, Oct 20, 1997

San Jose, Calif.--S3 continued its move into the mobile graphics accelerator market last week, here at the Microprocessor Forum '97, by introducing a 3-D graphics accelerator with embedded DRAM designed by S3. This is believed to be the first time that a graphics company has created its own DRAM design and incorporated it onto its graphics engine.

Targeted at mainstream notebook PCs, the graphics engine, dubbed the Virge/MXi, features two megabytes of S3-designed DRAM (S3RAM), provides both 2-D and 3-D performance and features an upgraded power management function. The Virge/MXi integrates Macrovision copy protection as well for protecting DVD and DuoView dual display content. The embedded DRAM accelerators are pin compatible with the second generation Virge/MX engines as well. S3 also integrated TV-out functions, DVD capabilities and multi-monitor technology for Microsoft Windows 9X.

"This is the only true engine that enables 3-D graphics with embedded DRAM. Other companies only have a 2-D engine and do not have Macrovision protection," asserted Andy Kelm, product marketing manager for mobile products at S3. "We have as many transistors on the Virge/MXi as an Intel processor for the mobile market. We expect to have 40 million transistors with embedded DRAM capability by next year."

S3 said it made the decision to design its own DRAM because it could deliver integrated DRAM capabilities quicker with its own design rather than having to rely upon another company's process that may or may not work correctly with S3's graphics accelerators. S3 said it will base the amount of DRAM integrated into its devices going forward on what is needed from the 3-D graphics market, not by how much DRAM is available in the market. United Microelectronics Company (UMC) is manufacturing the embedded DRAM accelerators on a 0.35-micron, four-layer metal process.

"We thought it was best to do the design ourselves because this way we could have one foundry do every process the way we wanted it to be done, not taking a separate process from another company and trying to migrate it to a foundry process," said Mr. Kelm.

The Virge/MXi graphics accelerator is sampling today, priced at $54 each in 10,000-unit quantities. S3 said it plans volume production beginning in 1H98. The die size of the Virge/MXi is less than 150 square millimeters.

NeoMagic--which has taken an aggressive role in the embedded memory market--gets its DRAM from Mitsubishi and then integrates that onto its accelerators, while Trident Microsystems and Chips & Technologies utilize Samsung Semiconductor DRAM processes. S3 claims it is the only mobile graphics accelerator vendor that is designing its own DRAM.

Mr. Kelm said the possibility exists that S3 may migrate this technology to the desktop market. However, the desktop market is very price sensitive and embedded DRAM devices are not so, until the price goes down appreciably, this won't happen. In the flat panel display (FPD) desktop market, however, price is not as much of an issue and S3 plans to introduce a device next year that will target this market.

According to Mike Feibus, principle analyst at Mercury Research, Tempe, Ariz., the fact that S3 is moving into this embedded DRAM market is not a surprise because the major players have seen how successful other companies have been at integrating DRAM onto a graphics accelerator.

"NeoMagic has pioneered this segment of the market and it has proven popular because it takes less space and power," said Mr. Feibus. "S3 has always been at the forefront of throwing the whole kitchen sink on one chip and adding 3-D acceleration, and they are at the leading edge of this trend now."

Meanwhile, in other Microprocessor Forum '97 developments, Billions of Operations Per Second (BOPS) introduced the ManArray multimedia architecture targeted at 3-D graphics, video compression, audio and other compute-intensive tasks. ManArray is the first product from the company that was founded by former IBM engineers.

The BOPS architecture is designed for a planned family of high-performance single-chip parallel processors based on a compute array of processing elements and controller sequence processors. BOPS is now licensing its family of cores to a limited number of partners, said Gerald G. Pechanek, CTO and co-founder of BOPS. The initial core is dubbed the Kitty Hawk, a 2x2 synthesizable core with development tools that is slated for availability in 1H98.