Xilinx plunging deeper into hybrid ASIC arena

Electronic News, Oct 20, 1997

San Jose, Calif.--Moving deeper into the custom logic market, Xilinx will today introduce a third generation of HardWired ASIC devices targeted at converting the company's field programmable gate arrays (FPGAs) into a masked gate array with all of the FPGA characteristics still on-chip.

Dubbed the XH3 HardWire ASIC series, the family features gate densities in the range of 15,000 to 225,000 gates and has the ability to migrate Xilinx intellectual property (IP) cores and FPGA features over to the masked ASIC from an FPGA. The XH3 architecture is based on Silicon Architects of Synopsys' cell-based array (CBA) sea-of-gates core, a Xilinx specific I/O ring, JTAG support, and logic to emulate the FPGA configuration modes built into the base silicon.

"The only thing the third tier conversion houses have over us now is price because they have the requirement of filling a fab somewhere," Chuck Fox, VP and GM of the high reliability business unit of Xilinx told Electronic News. "Some of these conversion guys don't make a profit on their products because they reduce the price so much just to fill their fabs. Since we don't have a fab to fill we can offer value and reliability while still generating a profit."

The XH3 series supports the XC4000 and XC5000 FPGA families and is based on a 0.5-micron, 5-volt CMOS technology. Xilinx's XH3 ASIC family is available now for conversion. A 50,000-gate XH3 device is priced at $6.50 in 250,000 units per year quantities with a non-recurring engineering (NRE) fee starting at $19,000. In addition to the NRE, another condition is the requirement of a minimum number in an order of devices. Depending upon the FPGAs, Xilinx's minimum order could be between 3,000 and 10,000 units, Mr. Fox said.

The conversion market has taken some interesting twists recently as industry observers revealed that Microchip has bowed out of the market entirely because of lack of revenues. Also, conversion start-up ClearLogic introduced itself last week as an FPGA alternative vendor (EN, Oct. 13) offering no NREs or minimums. Orbit Semiconductor, a wholly-owned subsidiary of the DII Group, also last week introduced a 300,000-gate conversion device targeted at high density FPGAs.

However, Xilinx said converting high density FPGAs is not as easy as it is with low density FPGAs. "Taking a piece of silicon and trying to move it to a hardwired process is not that hard at low density device," levels, said Shelly Davis, marketing manager for HardWire products at Xilinx.

Xilinx licensed the CBA technology roughly 18 months ago and had not used it in that time, deciding to develop its own core for its conversion process. This is the first implementation of the CBA technology in Xilinx's devices, said Ms. Davis. The XH3 technology allows a designer to eliminate the need for logic redesign, re-verification, and test vector generation that is normally required in a FPGA-to-ASIC conversion.

"What we are doing is not an ASIC redesign but we are taking the FPGA and modeling it and mapping it to the ASIC and attempting to stay as intact as possible to the original FPGA," said Mr. Fox. "A lot of conversions throw out everything that has been done to the FPGA and start over. That's what we want to avoid. Because of this, we plan on selling more FPGAs and more HardWire devices."

According to Mr. Fox, the HardWired business for Xilinx was five percent of the company's revenue last year. However, with the XH3 ASICs, Xilinx expects to increase that segment's revenue to approximately 10 percent in the near future, he added.

Next year, Xilinx plans to roll out its fourth generation of HardWired ASICs based on a 0.25-micron technology that will include advanced mapping and embedded cores. These ASICs will also be Xilinx FPGA-specific.