Motorola's MCore architecture makes debut

Electronic News, Oct 20, 1997 by Jim DeTar

Austin, Texas--Motorola unveiled the architecture for its new MCore 32-bit microRISC core at the Microprocessor Forum in San Jose last week. The formal unveiling followed a build-up that included a technology preview and roadmap at the company's bi-annual Horizons media event in Orlando, Florida (EN, Sept. 15) and the naming of the company's MCore software partners at the Embedded Systems Conference West (EN, Oct. 6).

"To develop this new core, we took a hard look at the future of low-power systems and the critical design issues that will determine their success," said Jim Thomas, VP and director of Motorola's MCore Technology Center.

The MCore architecture is a universal, load-store RISC engine that executes 16-bit instructions, and has a 32-bit internal data path for instructions and coding. The core contains a 16 entry, 32-bit general purpose register file, and processes instructions using a four-stage execution pipeline.

All memory operands are accessed through load and store instructions, transferring data between the general purpose registers and memory. Therefore, all computational activity takes place within the internal registers. Most instructions execute in one cycle; branches and memory access instructions require two cycles. The external bus, optimized for low cost 16-bit memory, can access 8-, 16 and 32-bit memories, and the programming model supports supervisor and user modes.

Kyle Harper, Motorola manager, wireless markets and programs, MCore Technology Center, said in an interview with Electronic News that the company will shortly announce the first licensees under the company's previously announced program to license the core to outside companies much as Advanced RISC Machines does with its ARM core. "A new architecture needs to be an open architecture," Mr. Harper said.

"We are in the process of franchising MCore. We are franchising this within SPS (Motorola's Semiconductor Products Sector), and the next logical step is to take MCore and license it externally. You will see Motorola offering it to those markets as a second source for pin-compatible products. What we're adding to the MCore program is licensing of the core to partners outside of Motorola for independent designs."

When pressed for a time table when the first licensees will be announced, Mr. Harper replied, "You will see more details of the licensing program before the end of the year. There is lots of heavy discussion."

The first MCore-based product will be a dual core integrated cellular baseband processor the company developed as a proprietary design for a customer. The device will include a M56600 16-bit DSP core and an MCore 32-bit RISC microcontroller core.

In addition, in the first quarter of 1998 there will be two standard parts families available, both on 0.36-micron process technology initially.

The first standard part, dubbed the Powerstrike 1, is targeted at battery powered, handheld systems, GPS systems, digital cameras and personal organizers. The Powerstrike 1 will sample in 1Q98 in a 100-pin TQFP package. A second part, an industrial control microcontroller dubbed MCU1, will be targeted at motor control, industrial process control, robotic and instrumentation applications and will sample in 3Q98, also in 100-pin TQFP.

Interrupt performance and flexibility are critical design issues for embedded controller systems. Motorola's MCore architecture is designed to support both vector and auto-vector interrupts, allowing the user the ability to define interrupt space. The core also contains dedicated logic to enable rapid task-switching and enhanced interrupt support, including both normal and high-priority interrupts.

Critical interrupts are handled with minimal overhead and latency, according to Motorola, via a full set of separate exception shadow registers and an alternate register file, which is a second general purpose register file. In many hand-held, low-power or interrupt and control-sensitive applications, this feature is said by the company to be able to eliminate the requirement for a DMA (direct memory access) controller.