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Electronic News, Oct 27, 1997 by Gale Morrison

San Francisco--The International Solid State Circuits Conference will take a different tack this February when communications ICs come into the fore, according to this year's organizers. Papers and presenters at the 45th International ISSCC, scheduled to run Feb. 3-7 at this city's Marriott Hotel, will have a "Global Communications" theme and, as usual, a wide ranging academic and industry R&D line-up.

On opening day, Tuesday, Feb. 3, the "xDSL Broadband Interactive Communications Via POTS" short course will concentrate on advanced digital subscriber loop (xDSL) communications over the existing twisted-pair copper infrastructure in the plain old telephone system (POTS), and conference organizers say xDSL modem architecture, technology, and analog/digital circuit tradeoffs will all get air time.

High-Speed Data On The Loop

The xDSL Broadband unit will have four segments. John Bingham of Amati Communications will present "High-Speed Data on the Subscriber Loop: xDSL;" David Johns of the University of Toronto will talk on "Passband HDSL and ADSL Circuits and Systems;" Damien Macq, Alcatel Mietec, brings a discussion of "DMT ADSL Circuits and Systems" to the conference; and finally, on Tuesday, John Cioffi of Stanford will present "Very-High-Speed Digital Subscriber Lines."

Six tutorials presented by members of ISSCC's Technical Program Committee will start Wednesday morning. The six will run throughout the day in parallel sessions so attendees can register for any combination of three. Presentor Bruce Bateman will talk on "High-Speed SRAM Design;" John Fattaruso on "Opamp Compensation for Low-Voltage, Mixed-Signal Designs;" Mehdi Hatamian on "FIR-1001: Architectures and Applications;" William Kaiser on "MEMS for the Circuit Designer;" and John Maneatis on "High-Speed Clocking for Large Digital ICs."

Embedded DRAM Workshop Planned

Concurrent to that, throughout Wednesday the IEEE Solid-State Circuits and Technology Committee is running a workshop on embedded DRAM technology, also at the Marriott. Jeffrey Dreibelbis of IBM is coordinating that. Executives from Memory Strategies International, Samsung, Mosaid, Toshiba, IBM, Mentor Graphics, Mitsubishi and a representative from an unnamed graphics concern will speak.

Thursday through Saturday will see the guts of ISSCC: some 25 technical paper sessions comprising a total of 159 papers. The plenary session will carry the "Global Communications" theme home with M. Nakamura of Hitachi hitting "Challenges in Semiconductor Technology for Multi-Megabit Network Services," J. Danneels of Alcatel Semiconductors (Zaventum, Belgium) addressing "GSM and Beyond: The Future of the Network Access," and K. Chaddha of SiRF Technology in Sunnyvale, Calif., covering "The Global Positioning System: Challenges in Bringing GPS to Mainstream Consumers."

On the die-shrinkage front, expect to see a 0.08-micron gate length CMOS test chip utilizing substrate over-biasing to achieve 40 picosecond gate delay at 0.5V. And on the interconnect horizon, look for an optical route to be discussed.

Highlights of the evening discussion sessions look to be "Three Decades of DRAM Development, Debates and Distinction," moderated by R. Foss, and "Global Communications: the Good, the Bad, and the Ugly," moderated by R. Walker. Thursday evening will also have a social hour.